100a2749dSAllen Martin /* 200a2749dSAllen Martin * (C) Copyright 2010,2011 300a2749dSAllen Martin * NVIDIA Corporation <www.nvidia.com> 400a2749dSAllen Martin * 500a2749dSAllen Martin * See file CREDITS for list of people who contributed to this 600a2749dSAllen Martin * project. 700a2749dSAllen Martin * 800a2749dSAllen Martin * This program is free software; you can redistribute it and/or 900a2749dSAllen Martin * modify it under the terms of the GNU General Public License as 1000a2749dSAllen Martin * published by the Free Software Foundation; either version 2 of 1100a2749dSAllen Martin * the License, or (at your option) any later version. 1200a2749dSAllen Martin * 1300a2749dSAllen Martin * This program is distributed in the hope that it will be useful, 1400a2749dSAllen Martin * but WITHOUT ANY WARRANTY; without even the implied warranty of 1500a2749dSAllen Martin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1600a2749dSAllen Martin * GNU General Public License for more details. 1700a2749dSAllen Martin * 1800a2749dSAllen Martin * You should have received a copy of the GNU General Public License 1900a2749dSAllen Martin * along with this program; if not, write to the Free Software 2000a2749dSAllen Martin * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 2100a2749dSAllen Martin * MA 02111-1307 USA 2200a2749dSAllen Martin */ 2300a2749dSAllen Martin 24*dc89ad14STom Warren #ifndef _TEGRA20_GP_PADCTRL_H_ 25*dc89ad14STom Warren #define _TEGRA20_GP_PADCTRL_H_ 26*dc89ad14STom Warren 27*dc89ad14STom Warren #include <asm/arch-tegra/gp_padctrl.h> 2800a2749dSAllen Martin 2900a2749dSAllen Martin /* APB_MISC_GP and padctrl registers */ 3000a2749dSAllen Martin struct apb_misc_gp_ctlr { 3100a2749dSAllen Martin u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ 3200a2749dSAllen Martin u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ 3300a2749dSAllen Martin u32 reserved0[22]; /* 0x08 - 0x5C: */ 3400a2749dSAllen Martin u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ 3500a2749dSAllen Martin u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ 3600a2749dSAllen Martin u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ 3700a2749dSAllen Martin u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */ 3800a2749dSAllen Martin u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ 3900a2749dSAllen Martin u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ 4000a2749dSAllen Martin u32 cdevcfg1; /* 0x78: APB_MISC_GP_CDEV1CFGPADCTRL */ 4100a2749dSAllen Martin u32 cdevcfg2; /* 0x7C: APB_MISC_GP_CDEV2CFGPADCTRL */ 4200a2749dSAllen Martin u32 csuscfg; /* 0x80: APB_MISC_GP_CSUSCFGPADCTRL */ 4300a2749dSAllen Martin u32 dap1cfg; /* 0x84: APB_MISC_GP_DAP1CFGPADCTRL */ 4400a2749dSAllen Martin u32 dap2cfg; /* 0x88: APB_MISC_GP_DAP2CFGPADCTRL */ 4500a2749dSAllen Martin u32 dap3cfg; /* 0x8C: APB_MISC_GP_DAP3CFGPADCTRL */ 4600a2749dSAllen Martin u32 dap4cfg; /* 0x90: APB_MISC_GP_DAP4CFGPADCTRL */ 4700a2749dSAllen Martin u32 dbgcfg; /* 0x94: APB_MISC_GP_DBGCFGPADCTRL */ 4800a2749dSAllen Martin u32 lcdcfg1; /* 0x98: APB_MISC_GP_LCDCFG1PADCTRL */ 4900a2749dSAllen Martin u32 lcdcfg2; /* 0x9C: APB_MISC_GP_LCDCFG2PADCTRL */ 5000a2749dSAllen Martin u32 sdmmc2_cfg; /* 0xA0: APB_MISC_GP_SDMMC2CFGPADCTRL */ 5100a2749dSAllen Martin u32 sdmmc3_cfg; /* 0xA4: APB_MISC_GP_SDMMC3CFGPADCTRL */ 5200a2749dSAllen Martin u32 spicfg; /* 0xA8: APB_MISC_GP_SPICFGPADCTRL */ 5300a2749dSAllen Martin u32 uaacfg; /* 0xAC: APB_MISC_GP_UAACFGPADCTRL */ 5400a2749dSAllen Martin u32 uabcfg; /* 0xB0: APB_MISC_GP_UABCFGPADCTRL */ 5500a2749dSAllen Martin u32 uart2cfg; /* 0xB4: APB_MISC_GP_UART2CFGPADCTRL */ 5600a2749dSAllen Martin u32 uart3cfg; /* 0xB8: APB_MISC_GP_UART3CFGPADCTRL */ 5700a2749dSAllen Martin u32 vicfg1; /* 0xBC: APB_MISC_GP_VICFG1PADCTRL */ 5800a2749dSAllen Martin u32 vicfg2; /* 0xC0: APB_MISC_GP_VICFG2PADCTRL */ 5900a2749dSAllen Martin u32 xm2cfga; /* 0xC4: APB_MISC_GP_XM2CFGAPADCTRL */ 6000a2749dSAllen Martin u32 xm2cfgc; /* 0xC8: APB_MISC_GP_XM2CFGCPADCTRL */ 6100a2749dSAllen Martin u32 xm2cfgd; /* 0xCC: APB_MISC_GP_XM2CFGDPADCTRL */ 6200a2749dSAllen Martin u32 xm2clkcfg; /* 0xD0: APB_MISC_GP_XM2CLKCFGPADCTRL */ 6300a2749dSAllen Martin u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */ 6400a2749dSAllen Martin }; 6500a2749dSAllen Martin 66*dc89ad14STom Warren #endif /* _TEGRA20_GP_PADCTRL_H_ */ 67