1*00a2749dSAllen Martin /* 2*00a2749dSAllen Martin * (C) Copyright 2010,2011 3*00a2749dSAllen Martin * NVIDIA Corporation <www.nvidia.com> 4*00a2749dSAllen Martin * 5*00a2749dSAllen Martin * See file CREDITS for list of people who contributed to this 6*00a2749dSAllen Martin * project. 7*00a2749dSAllen Martin * 8*00a2749dSAllen Martin * This program is free software; you can redistribute it and/or 9*00a2749dSAllen Martin * modify it under the terms of the GNU General Public License as 10*00a2749dSAllen Martin * published by the Free Software Foundation; either version 2 of 11*00a2749dSAllen Martin * the License, or (at your option) any later version. 12*00a2749dSAllen Martin * 13*00a2749dSAllen Martin * This program is distributed in the hope that it will be useful, 14*00a2749dSAllen Martin * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*00a2749dSAllen Martin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*00a2749dSAllen Martin * GNU General Public License for more details. 17*00a2749dSAllen Martin * 18*00a2749dSAllen Martin * You should have received a copy of the GNU General Public License 19*00a2749dSAllen Martin * along with this program; if not, write to the Free Software 20*00a2749dSAllen Martin * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*00a2749dSAllen Martin * MA 02111-1307 USA 22*00a2749dSAllen Martin */ 23*00a2749dSAllen Martin 24*00a2749dSAllen Martin #ifndef _GP_PADCTRL_H_ 25*00a2749dSAllen Martin #define _GP_PADCTRL_H_ 26*00a2749dSAllen Martin 27*00a2749dSAllen Martin /* APB_MISC_GP and padctrl registers */ 28*00a2749dSAllen Martin struct apb_misc_gp_ctlr { 29*00a2749dSAllen Martin u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ 30*00a2749dSAllen Martin u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ 31*00a2749dSAllen Martin u32 reserved0[22]; /* 0x08 - 0x5C: */ 32*00a2749dSAllen Martin u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ 33*00a2749dSAllen Martin u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ 34*00a2749dSAllen Martin u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ 35*00a2749dSAllen Martin u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */ 36*00a2749dSAllen Martin u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ 37*00a2749dSAllen Martin u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ 38*00a2749dSAllen Martin u32 cdevcfg1; /* 0x78: APB_MISC_GP_CDEV1CFGPADCTRL */ 39*00a2749dSAllen Martin u32 cdevcfg2; /* 0x7C: APB_MISC_GP_CDEV2CFGPADCTRL */ 40*00a2749dSAllen Martin u32 csuscfg; /* 0x80: APB_MISC_GP_CSUSCFGPADCTRL */ 41*00a2749dSAllen Martin u32 dap1cfg; /* 0x84: APB_MISC_GP_DAP1CFGPADCTRL */ 42*00a2749dSAllen Martin u32 dap2cfg; /* 0x88: APB_MISC_GP_DAP2CFGPADCTRL */ 43*00a2749dSAllen Martin u32 dap3cfg; /* 0x8C: APB_MISC_GP_DAP3CFGPADCTRL */ 44*00a2749dSAllen Martin u32 dap4cfg; /* 0x90: APB_MISC_GP_DAP4CFGPADCTRL */ 45*00a2749dSAllen Martin u32 dbgcfg; /* 0x94: APB_MISC_GP_DBGCFGPADCTRL */ 46*00a2749dSAllen Martin u32 lcdcfg1; /* 0x98: APB_MISC_GP_LCDCFG1PADCTRL */ 47*00a2749dSAllen Martin u32 lcdcfg2; /* 0x9C: APB_MISC_GP_LCDCFG2PADCTRL */ 48*00a2749dSAllen Martin u32 sdmmc2_cfg; /* 0xA0: APB_MISC_GP_SDMMC2CFGPADCTRL */ 49*00a2749dSAllen Martin u32 sdmmc3_cfg; /* 0xA4: APB_MISC_GP_SDMMC3CFGPADCTRL */ 50*00a2749dSAllen Martin u32 spicfg; /* 0xA8: APB_MISC_GP_SPICFGPADCTRL */ 51*00a2749dSAllen Martin u32 uaacfg; /* 0xAC: APB_MISC_GP_UAACFGPADCTRL */ 52*00a2749dSAllen Martin u32 uabcfg; /* 0xB0: APB_MISC_GP_UABCFGPADCTRL */ 53*00a2749dSAllen Martin u32 uart2cfg; /* 0xB4: APB_MISC_GP_UART2CFGPADCTRL */ 54*00a2749dSAllen Martin u32 uart3cfg; /* 0xB8: APB_MISC_GP_UART3CFGPADCTRL */ 55*00a2749dSAllen Martin u32 vicfg1; /* 0xBC: APB_MISC_GP_VICFG1PADCTRL */ 56*00a2749dSAllen Martin u32 vicfg2; /* 0xC0: APB_MISC_GP_VICFG2PADCTRL */ 57*00a2749dSAllen Martin u32 xm2cfga; /* 0xC4: APB_MISC_GP_XM2CFGAPADCTRL */ 58*00a2749dSAllen Martin u32 xm2cfgc; /* 0xC8: APB_MISC_GP_XM2CFGCPADCTRL */ 59*00a2749dSAllen Martin u32 xm2cfgd; /* 0xCC: APB_MISC_GP_XM2CFGDPADCTRL */ 60*00a2749dSAllen Martin u32 xm2clkcfg; /* 0xD0: APB_MISC_GP_XM2CLKCFGPADCTRL */ 61*00a2749dSAllen Martin u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */ 62*00a2749dSAllen Martin }; 63*00a2749dSAllen Martin 64*00a2749dSAllen Martin /* bit fields definitions for APB_MISC_GP_HIDREV register */ 65*00a2749dSAllen Martin #define HIDREV_CHIPID_SHIFT 8 66*00a2749dSAllen Martin #define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT) 67*00a2749dSAllen Martin #define HIDREV_MAJORPREV_SHIFT 4 68*00a2749dSAllen Martin #define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT) 69*00a2749dSAllen Martin 70*00a2749dSAllen Martin /* CHIPID field returned from APB_MISC_GP_HIDREV register */ 71*00a2749dSAllen Martin #define CHIPID_TEGRA20 0x20 72*00a2749dSAllen Martin 73*00a2749dSAllen Martin #endif 74