100a2749dSAllen Martin /* 200a2749dSAllen Martin * Copyright (c) 2011 The Chromium OS Authors. 300a2749dSAllen Martin * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com> 400a2749dSAllen Martin * 5*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 600a2749dSAllen Martin */ 700a2749dSAllen Martin 800a2749dSAllen Martin #ifndef _ARCH_EMC_H_ 900a2749dSAllen Martin #define _ARCH_EMC_H_ 1000a2749dSAllen Martin 1100a2749dSAllen Martin #include <asm/types.h> 1200a2749dSAllen Martin 1300a2749dSAllen Martin #define TEGRA_EMC_NUM_REGS 46 1400a2749dSAllen Martin 1500a2749dSAllen Martin /* EMC Registers */ 1600a2749dSAllen Martin struct emc_ctlr { 1700a2749dSAllen Martin u32 cfg; /* 0x00: EMC_CFG */ 1800a2749dSAllen Martin u32 reserved0[3]; /* 0x04 ~ 0x0C */ 1900a2749dSAllen Martin u32 adr_cfg; /* 0x10: EMC_ADR_CFG */ 2000a2749dSAllen Martin u32 adr_cfg1; /* 0x14: EMC_ADR_CFG_1 */ 2100a2749dSAllen Martin u32 reserved1[2]; /* 0x18 ~ 0x18 */ 2200a2749dSAllen Martin u32 refresh_ctrl; /* 0x20: EMC_REFCTRL */ 2300a2749dSAllen Martin u32 pin; /* 0x24: EMC_PIN */ 2400a2749dSAllen Martin u32 timing_ctrl; /* 0x28: EMC_TIMING_CONTROL */ 2500a2749dSAllen Martin u32 rc; /* 0x2C: EMC_RC */ 2600a2749dSAllen Martin u32 rfc; /* 0x30: EMC_RFC */ 2700a2749dSAllen Martin u32 ras; /* 0x34: EMC_RAS */ 2800a2749dSAllen Martin u32 rp; /* 0x38: EMC_RP */ 2900a2749dSAllen Martin u32 r2w; /* 0x3C: EMC_R2W */ 3000a2749dSAllen Martin u32 w2r; /* 0x40: EMC_W2R */ 3100a2749dSAllen Martin u32 r2p; /* 0x44: EMC_R2P */ 3200a2749dSAllen Martin u32 w2p; /* 0x48: EMC_W2P */ 3300a2749dSAllen Martin u32 rd_rcd; /* 0x4C: EMC_RD_RCD */ 3400a2749dSAllen Martin u32 wd_rcd; /* 0x50: EMC_WD_RCD */ 3500a2749dSAllen Martin u32 rrd; /* 0x54: EMC_RRD */ 3600a2749dSAllen Martin u32 rext; /* 0x58: EMC_REXT */ 3700a2749dSAllen Martin u32 wdv; /* 0x5C: EMC_WDV */ 3800a2749dSAllen Martin u32 quse; /* 0x60: EMC_QUSE */ 3900a2749dSAllen Martin u32 qrst; /* 0x64: EMC_QRST */ 4000a2749dSAllen Martin u32 qsafe; /* 0x68: EMC_QSAFE */ 4100a2749dSAllen Martin u32 rdv; /* 0x6C: EMC_RDV */ 4200a2749dSAllen Martin u32 refresh; /* 0x70: EMC_REFRESH */ 4300a2749dSAllen Martin u32 burst_refresh_num; /* 0x74: EMC_BURST_REFRESH_NUM */ 4400a2749dSAllen Martin u32 pdex2wr; /* 0x78: EMC_PDEX2WR */ 4500a2749dSAllen Martin u32 pdex2rd; /* 0x7c: EMC_PDEX2RD */ 4600a2749dSAllen Martin u32 pchg2pden; /* 0x80: EMC_PCHG2PDEN */ 4700a2749dSAllen Martin u32 act2pden; /* 0x84: EMC_ACT2PDEN */ 4800a2749dSAllen Martin u32 ar2pden; /* 0x88: EMC_AR2PDEN */ 4900a2749dSAllen Martin u32 rw2pden; /* 0x8C: EMC_RW2PDEN */ 5000a2749dSAllen Martin u32 txsr; /* 0x90: EMC_TXSR */ 5100a2749dSAllen Martin u32 tcke; /* 0x94: EMC_TCKE */ 5200a2749dSAllen Martin u32 tfaw; /* 0x98: EMC_TFAW */ 5300a2749dSAllen Martin u32 trpab; /* 0x9C: EMC_TRPAB */ 5400a2749dSAllen Martin u32 tclkstable; /* 0xA0: EMC_TCLKSTABLE */ 5500a2749dSAllen Martin u32 tclkstop; /* 0xA4: EMC_TCLKSTOP */ 5600a2749dSAllen Martin u32 trefbw; /* 0xA8: EMC_TREFBW */ 5700a2749dSAllen Martin u32 quse_extra; /* 0xAC: EMC_QUSE_EXTRA */ 5800a2749dSAllen Martin u32 odt_write; /* 0xB0: EMC_ODT_WRITE */ 5900a2749dSAllen Martin u32 odt_read; /* 0xB4: EMC_ODT_READ */ 6000a2749dSAllen Martin u32 reserved2[5]; /* 0xB8 ~ 0xC8 */ 6100a2749dSAllen Martin u32 mrs; /* 0xCC: EMC_MRS */ 6200a2749dSAllen Martin u32 emrs; /* 0xD0: EMC_EMRS */ 6300a2749dSAllen Martin u32 ref; /* 0xD4: EMC_REF */ 6400a2749dSAllen Martin u32 pre; /* 0xD8: EMC_PRE */ 6500a2749dSAllen Martin u32 nop; /* 0xDC: EMC_NOP */ 6600a2749dSAllen Martin u32 self_ref; /* 0xE0: EMC_SELF_REF */ 6700a2749dSAllen Martin u32 dpd; /* 0xE4: EMC_DPD */ 6800a2749dSAllen Martin u32 mrw; /* 0xE8: EMC_MRW */ 6900a2749dSAllen Martin u32 mrr; /* 0xEC: EMC_MRR */ 7000a2749dSAllen Martin u32 reserved3; /* 0xF0: */ 7100a2749dSAllen Martin u32 fbio_cfg1; /* 0xF4: EMC_FBIO_CFG1 */ 7200a2749dSAllen Martin u32 fbio_dqsib_dly; /* 0xF8: EMC_FBIO_DQSIB_DLY */ 7300a2749dSAllen Martin u32 fbio_dqsib_dly_msb; /* 0xFC: EMC_FBIO_DQSIB_DLY_MSG */ 7400a2749dSAllen Martin u32 fbio_spare; /* 0x100: SBIO_SPARE */ 7500a2749dSAllen Martin /* There are more registers ... */ 7600a2749dSAllen Martin }; 7700a2749dSAllen Martin 7800a2749dSAllen Martin /** 7900a2749dSAllen Martin * Set up the EMC for the given rate. The timing parameters are retrieved 8000a2749dSAllen Martin * from the device tree "nvidia,tegra20-emc" node and its 8100a2749dSAllen Martin * "nvidia,tegra20-emc-table" sub-nodes. 8200a2749dSAllen Martin * 8300a2749dSAllen Martin * @param blob Device tree blob 8400a2749dSAllen Martin * @param rate Clock speed of memory controller in Hz (=2x memory bus rate) 8500a2749dSAllen Martin * @return 0 if ok, else -ve error code (look in emc.c to decode it) 8600a2749dSAllen Martin */ 8700a2749dSAllen Martin int tegra_set_emc(const void *blob, unsigned rate); 8800a2749dSAllen Martin 8900a2749dSAllen Martin /** 9000a2749dSAllen Martin * Get a pointer to the EMC controller from the device tree. 9100a2749dSAllen Martin * 9200a2749dSAllen Martin * @param blob Device tree blob 9300a2749dSAllen Martin * @return pointer to EMC controller 9400a2749dSAllen Martin */ 9500a2749dSAllen Martin struct emc_ctlr *emc_get_controller(const void *blob); 9600a2749dSAllen Martin 9700a2749dSAllen Martin #endif 98