1*87540de3SWei Ni /* 2*87540de3SWei Ni * (C) Copyright 2010 3*87540de3SWei Ni * NVIDIA Corporation <www.nvidia.com> 4*87540de3SWei Ni * 5*87540de3SWei Ni * See file CREDITS for list of people who contributed to this 6*87540de3SWei Ni * project. 7*87540de3SWei Ni * 8*87540de3SWei Ni * This program is free software; you can redistribute it and/or 9*87540de3SWei Ni * modify it under the terms of the GNU General Public License as 10*87540de3SWei Ni * published by the Free Software Foundation; either version 2 of 11*87540de3SWei Ni * the License, or (at your option) any later version. 12*87540de3SWei Ni * 13*87540de3SWei Ni * This program is distributed in the hope that it will be useful, 14*87540de3SWei Ni * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*87540de3SWei Ni * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*87540de3SWei Ni * GNU General Public License for more details. 17*87540de3SWei Ni * 18*87540de3SWei Ni * You should have received a copy of the GNU General Public License 19*87540de3SWei Ni * along with this program; if not, write to the Free Software 20*87540de3SWei Ni * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*87540de3SWei Ni * MA 02111-1307 USA 22*87540de3SWei Ni */ 23*87540de3SWei Ni 24*87540de3SWei Ni #ifndef __ASM_ARCH_TEGRA_DISPLAY_H 25*87540de3SWei Ni #define __ASM_ARCH_TEGRA_DISPLAY_H 26*87540de3SWei Ni 27*87540de3SWei Ni #include <asm/arch/dc.h> 28*87540de3SWei Ni #include <fdtdec.h> 29*87540de3SWei Ni 30*87540de3SWei Ni /* This holds information about a window which can be displayed */ 31*87540de3SWei Ni struct disp_ctl_win { 32*87540de3SWei Ni enum win_color_depth_id fmt; /* Color depth/format */ 33*87540de3SWei Ni unsigned bpp; /* Bits per pixel */ 34*87540de3SWei Ni phys_addr_t phys_addr; /* Physical address in memory */ 35*87540de3SWei Ni unsigned x; /* Horizontal address offset (bytes) */ 36*87540de3SWei Ni unsigned y; /* Veritical address offset (bytes) */ 37*87540de3SWei Ni unsigned w; /* Width of source window */ 38*87540de3SWei Ni unsigned h; /* Height of source window */ 39*87540de3SWei Ni unsigned stride; /* Number of bytes per line */ 40*87540de3SWei Ni unsigned out_x; /* Left edge of output window (col) */ 41*87540de3SWei Ni unsigned out_y; /* Top edge of output window (row) */ 42*87540de3SWei Ni unsigned out_w; /* Width of output window in pixels */ 43*87540de3SWei Ni unsigned out_h; /* Height of output window in pixels */ 44*87540de3SWei Ni }; 45*87540de3SWei Ni 46*87540de3SWei Ni #define FDT_LCD_TIMINGS 4 47*87540de3SWei Ni 48*87540de3SWei Ni enum { 49*87540de3SWei Ni FDT_LCD_TIMING_REF_TO_SYNC, 50*87540de3SWei Ni FDT_LCD_TIMING_SYNC_WIDTH, 51*87540de3SWei Ni FDT_LCD_TIMING_BACK_PORCH, 52*87540de3SWei Ni FDT_LCD_TIMING_FRONT_PORCH, 53*87540de3SWei Ni 54*87540de3SWei Ni FDT_LCD_TIMING_COUNT, 55*87540de3SWei Ni }; 56*87540de3SWei Ni 57*87540de3SWei Ni enum lcd_cache_t { 58*87540de3SWei Ni FDT_LCD_CACHE_OFF = 0, 59*87540de3SWei Ni FDT_LCD_CACHE_WRITE_THROUGH = 1 << 0, 60*87540de3SWei Ni FDT_LCD_CACHE_WRITE_BACK = 1 << 1, 61*87540de3SWei Ni FDT_LCD_CACHE_FLUSH = 1 << 2, 62*87540de3SWei Ni FDT_LCD_CACHE_WRITE_BACK_FLUSH = FDT_LCD_CACHE_WRITE_BACK | 63*87540de3SWei Ni FDT_LCD_CACHE_FLUSH, 64*87540de3SWei Ni }; 65*87540de3SWei Ni 66*87540de3SWei Ni /* Information about the display controller */ 67*87540de3SWei Ni struct fdt_disp_config { 68*87540de3SWei Ni int valid; /* config is valid */ 69*87540de3SWei Ni int width; /* width in pixels */ 70*87540de3SWei Ni int height; /* height in pixels */ 71*87540de3SWei Ni int bpp; /* number of bits per pixel */ 72*87540de3SWei Ni 73*87540de3SWei Ni /* 74*87540de3SWei Ni * log2 of number of bpp, in general, unless it bpp is 24 in which 75*87540de3SWei Ni * case this field holds 24 also! This is a U-Boot thing. 76*87540de3SWei Ni */ 77*87540de3SWei Ni int log2_bpp; 78*87540de3SWei Ni struct disp_ctlr *disp; /* Display controller to use */ 79*87540de3SWei Ni fdt_addr_t frame_buffer; /* Address of frame buffer */ 80*87540de3SWei Ni unsigned pixel_clock; /* Pixel clock in Hz */ 81*87540de3SWei Ni uint horiz_timing[FDT_LCD_TIMING_COUNT]; /* Horizontal timing */ 82*87540de3SWei Ni uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */ 83*87540de3SWei Ni int panel_node; /* node offset of panel information */ 84*87540de3SWei Ni }; 85*87540de3SWei Ni 86*87540de3SWei Ni /* Information about the LCD panel */ 87*87540de3SWei Ni struct fdt_panel_config { 88*87540de3SWei Ni int pwm_channel; /* PWM channel to use for backlight */ 89*87540de3SWei Ni enum lcd_cache_t cache_type; 90*87540de3SWei Ni 91*87540de3SWei Ni struct fdt_gpio_state backlight_en; /* GPIO for backlight enable */ 92*87540de3SWei Ni struct fdt_gpio_state lvds_shutdown; /* GPIO for lvds shutdown */ 93*87540de3SWei Ni struct fdt_gpio_state backlight_vdd; /* GPIO for backlight vdd */ 94*87540de3SWei Ni struct fdt_gpio_state panel_vdd; /* GPIO for panel vdd */ 95*87540de3SWei Ni /* 96*87540de3SWei Ni * Panel required timings 97*87540de3SWei Ni * Timing 1: delay between panel_vdd-rise and data-rise 98*87540de3SWei Ni * Timing 2: delay between data-rise and backlight_vdd-rise 99*87540de3SWei Ni * Timing 3: delay between backlight_vdd and pwm-rise 100*87540de3SWei Ni * Timing 4: delay between pwm-rise and backlight_en-rise 101*87540de3SWei Ni */ 102*87540de3SWei Ni uint panel_timings[FDT_LCD_TIMINGS]; 103*87540de3SWei Ni }; 104*87540de3SWei Ni 105*87540de3SWei Ni /** 106*87540de3SWei Ni * Register a new display based on device tree configuration. 107*87540de3SWei Ni * 108*87540de3SWei Ni * The frame buffer can be positioned by U-Boot or overriden by the fdt. 109*87540de3SWei Ni * You should pass in the U-Boot address here, and check the contents of 110*87540de3SWei Ni * struct fdt_disp_config to see what was actually chosen. 111*87540de3SWei Ni * 112*87540de3SWei Ni * @param blob Device tree blob 113*87540de3SWei Ni * @param default_lcd_base Default address of LCD frame buffer 114*87540de3SWei Ni * @return 0 if ok, -1 on error (unsupported bits per pixel) 115*87540de3SWei Ni */ 116*87540de3SWei Ni int tegra_display_probe(const void *blob, void *default_lcd_base); 117*87540de3SWei Ni 118*87540de3SWei Ni /** 119*87540de3SWei Ni * Return the current display configuration 120*87540de3SWei Ni * 121*87540de3SWei Ni * @return pointer to display configuration, or NULL if there is no valid 122*87540de3SWei Ni * config 123*87540de3SWei Ni */ 124*87540de3SWei Ni struct fdt_disp_config *tegra_display_get_config(void); 125*87540de3SWei Ni 126*87540de3SWei Ni /** 127*87540de3SWei Ni * Perform the next stage of the LCD init if it is time to do so. 128*87540de3SWei Ni * 129*87540de3SWei Ni * LCD init can be time-consuming because of the number of delays we need 130*87540de3SWei Ni * while waiting for the backlight power supply, etc. This function can 131*87540de3SWei Ni * be called at various times during U-Boot operation to advance the 132*87540de3SWei Ni * initialization of the LCD to the next stage if sufficient time has 133*87540de3SWei Ni * passed since the last stage. It keeps track of what stage it is up to 134*87540de3SWei Ni * and the time that it is permitted to move to the next stage. 135*87540de3SWei Ni * 136*87540de3SWei Ni * The final call should have wait=1 to complete the init. 137*87540de3SWei Ni * 138*87540de3SWei Ni * @param blob fdt blob containing LCD information 139*87540de3SWei Ni * @param wait 1 to wait until all init is complete, and then return 140*87540de3SWei Ni * 0 to return immediately, potentially doing nothing if it is 141*87540de3SWei Ni * not yet time for the next init. 142*87540de3SWei Ni */ 143*87540de3SWei Ni int tegra_lcd_check_next_stage(const void *blob, int wait); 144*87540de3SWei Ni 145*87540de3SWei Ni /** 146*87540de3SWei Ni * Set up the maximum LCD size so we can size the frame buffer. 147*87540de3SWei Ni * 148*87540de3SWei Ni * @param blob fdt blob containing LCD information 149*87540de3SWei Ni */ 150*87540de3SWei Ni void tegra_lcd_early_init(const void *blob); 151*87540de3SWei Ni 152*87540de3SWei Ni #endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ 153