xref: /rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra20/clock.h (revision a74a4a86a53726ba17de8ab863bec1cd60cf545e)
100a2749dSAllen Martin /*
200a2749dSAllen Martin  * Copyright (c) 2011 The Chromium OS Authors.
300a2749dSAllen Martin  *
41a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
500a2749dSAllen Martin  */
600a2749dSAllen Martin 
7150c2493STom Warren /* Tegra20 clock control functions */
800a2749dSAllen Martin 
9150c2493STom Warren #ifndef _TEGRA20_CLOCK_H
10150c2493STom Warren #define _TEGRA20_CLOCK_H
1100a2749dSAllen Martin 
12150c2493STom Warren #include <asm/arch-tegra/clock.h>
1300a2749dSAllen Martin 
14f29f086aSTom Warren /* CLK_RST_CONTROLLER_OSC_CTRL_0 */
15f29f086aSTom Warren #define OSC_FREQ_SHIFT          30
16f29f086aSTom Warren #define OSC_FREQ_MASK           (3U << OSC_FREQ_SHIFT)
17f29f086aSTom Warren 
18*a7230745SThierry Reding int tegra_plle_enable(void);
19*a7230745SThierry Reding 
20150c2493STom Warren #endif	/* _TEGRA20_CLOCK_H */
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