1*999c6bafSTom Warren /* 2*999c6bafSTom Warren * (C) Copyright 2013 3*999c6bafSTom Warren * NVIDIA Corporation <www.nvidia.com> 4*999c6bafSTom Warren * 5*999c6bafSTom Warren * SPDX-License-Identifier: GPL-2.0+ 6*999c6bafSTom Warren */ 7*999c6bafSTom Warren 8*999c6bafSTom Warren #ifndef _TEGRA124_H_ 9*999c6bafSTom Warren #define _TEGRA124_H_ 10*999c6bafSTom Warren 11*999c6bafSTom Warren #define NV_PA_SDRAM_BASE 0x80000000 12*999c6bafSTom Warren #define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ 13*999c6bafSTom Warren #define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */ 14*999c6bafSTom Warren #define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */ 15*999c6bafSTom Warren 16*999c6bafSTom Warren #include <asm/arch-tegra/tegra.h> 17*999c6bafSTom Warren 18*999c6bafSTom Warren #define BCT_ODMDATA_OFFSET 1704 /* offset to ODMDATA word */ 19*999c6bafSTom Warren 20*999c6bafSTom Warren #undef NVBOOTINFOTABLE_BCTSIZE 21*999c6bafSTom Warren #undef NVBOOTINFOTABLE_BCTPTR 22*999c6bafSTom Warren #define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ 23*999c6bafSTom Warren #define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ 24*999c6bafSTom Warren 25*999c6bafSTom Warren #define MAX_NUM_CPU 4 26*999c6bafSTom Warren #define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8) 27*999c6bafSTom Warren 28*999c6bafSTom Warren #define TEGRA_USB1_BASE 0x7D000000 29*999c6bafSTom Warren 30*999c6bafSTom Warren #endif /* _TEGRA124_H_ */ 31