1*999c6bafSTom Warren /* 2*999c6bafSTom Warren * (C) Copyright 2013 3*999c6bafSTom Warren * NVIDIA Corporation <www.nvidia.com> 4*999c6bafSTom Warren * 5*999c6bafSTom Warren * SPDX-License-Identifier: GPL-2.0+ 6*999c6bafSTom Warren */ 7*999c6bafSTom Warren 8*999c6bafSTom Warren #ifndef _TEGRA124_SYSCTR_H_ 9*999c6bafSTom Warren #define _TEGRA124_SYSCTR_H_ 10*999c6bafSTom Warren 11*999c6bafSTom Warren struct sysctr_ctlr { 12*999c6bafSTom Warren u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ 13*999c6bafSTom Warren u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ 14*999c6bafSTom Warren u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ 15*999c6bafSTom Warren u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ 16*999c6bafSTom Warren u32 reserved1[4]; /* 0x10 - 0x1C */ 17*999c6bafSTom Warren u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ 18*999c6bafSTom Warren u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ 19*999c6bafSTom Warren u32 reserved2[1002]; /* 0x28 - 0xFCC */ 20*999c6bafSTom Warren u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ 21*999c6bafSTom Warren }; 22*999c6bafSTom Warren 23*999c6bafSTom Warren #define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ 24*999c6bafSTom Warren #define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ 25*999c6bafSTom Warren 26*999c6bafSTom Warren #endif /* _TEGRA124_SYSCTR_H_ */ 27