1999c6bafSTom Warren /* 2999c6bafSTom Warren * (C) Copyright 2010-2013 3999c6bafSTom Warren * NVIDIA Corporation <www.nvidia.com> 4999c6bafSTom Warren * 5999c6bafSTom Warren * SPDX-License-Identifier: GPL-2.0+ 6999c6bafSTom Warren */ 7999c6bafSTom Warren 8999c6bafSTom Warren #ifndef _TEGRA124_FLOW_H_ 9999c6bafSTom Warren #define _TEGRA124_FLOW_H_ 10999c6bafSTom Warren 11999c6bafSTom Warren struct flow_ctlr { 12999c6bafSTom Warren u32 halt_cpu_events; /* offset 0x00 */ 13999c6bafSTom Warren u32 halt_cop_events; /* offset 0x04 */ 14999c6bafSTom Warren u32 cpu_csr; /* offset 0x08 */ 15999c6bafSTom Warren u32 cop_csr; /* offset 0x0c */ 16999c6bafSTom Warren u32 xrq_events; /* offset 0x10 */ 17999c6bafSTom Warren u32 halt_cpu1_events; /* offset 0x14 */ 18999c6bafSTom Warren u32 cpu1_csr; /* offset 0x18 */ 19999c6bafSTom Warren u32 halt_cpu2_events; /* offset 0x1c */ 20999c6bafSTom Warren u32 cpu2_csr; /* offset 0x20 */ 21999c6bafSTom Warren u32 halt_cpu3_events; /* offset 0x24 */ 22999c6bafSTom Warren u32 cpu3_csr; /* offset 0x28 */ 23999c6bafSTom Warren u32 cluster_control; /* offset 0x2c */ 24999c6bafSTom Warren u32 halt_cop1_events; /* offset 0x30 */ 25999c6bafSTom Warren u32 halt_cop1_csr; /* offset 0x34 */ 26999c6bafSTom Warren u32 cpu_pwr_csr; /* offset 0x38 */ 27999c6bafSTom Warren u32 mpid; /* offset 0x3c */ 28999c6bafSTom Warren u32 ram_repair; /* offset 0x40 */ 29*701b7b1dSSimon Glass u32 flow_dbg_sel; /* offset 0x44 */ 30*701b7b1dSSimon Glass u32 flow_dbg_cnt0; /* offset 0x48 */ 31*701b7b1dSSimon Glass u32 flow_dbg_cnt1; /* offset 0x4c */ 32*701b7b1dSSimon Glass u32 flow_dbg_qual; /* offset 0x50 */ 33*701b7b1dSSimon Glass u32 flow_ctlr_spare; /* offset 0x54 */ 34*701b7b1dSSimon Glass u32 ram_repair_cluster1;/* offset 0x58 */ 35999c6bafSTom Warren }; 36999c6bafSTom Warren 37999c6bafSTom Warren /* HALT_COP_EVENTS_0, 0x04 */ 38999c6bafSTom Warren #define EVENT_MSEC (1 << 24) 39999c6bafSTom Warren #define EVENT_USEC (1 << 25) 40999c6bafSTom Warren #define EVENT_JTAG (1 << 28) 41999c6bafSTom Warren #define EVENT_MODE_STOP (2 << 29) 42999c6bafSTom Warren 43999c6bafSTom Warren /* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ 44999c6bafSTom Warren #define ACTIVE_LP (1 << 0) 45999c6bafSTom Warren 46ffdf9f9aSJan Kiszka /* CPUn_CSR_0 */ 47ffdf9f9aSJan Kiszka #define CSR_ENABLE (1 << 0) 48ffdf9f9aSJan Kiszka #define CSR_IMMEDIATE_WAKE (1 << 3) 49ffdf9f9aSJan Kiszka #define CSR_WAIT_WFI_SHIFT 8 50ffdf9f9aSJan Kiszka #define CSR_PWR_OFF_STS (1 << 16) 51ffdf9f9aSJan Kiszka 52*701b7b1dSSimon Glass /* RAM_REPAIR, 0x40, 0x58 */ 53*701b7b1dSSimon Glass enum { 54*701b7b1dSSimon Glass RAM_REPAIR_REQ = 0x1 << 0, 55*701b7b1dSSimon Glass RAM_REPAIR_STS = 0x1 << 1, 56*701b7b1dSSimon Glass }; 57*701b7b1dSSimon Glass 58999c6bafSTom Warren #endif /* _TEGRA124_FLOW_H_ */ 59