xref: /rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra114/sysctr.h (revision b40f734af9fdc47a0993f1f94f32d40a86f30587)
1*b40f734aSTom Warren /*
2*b40f734aSTom Warren  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
3*b40f734aSTom Warren  *
4*b40f734aSTom Warren  * This program is free software; you can redistribute it and/or modify it
5*b40f734aSTom Warren  * under the terms and conditions of the GNU General Public License,
6*b40f734aSTom Warren  * version 2, as published by the Free Software Foundation.
7*b40f734aSTom Warren  *
8*b40f734aSTom Warren  * This program is distributed in the hope it will be useful, but WITHOUT
9*b40f734aSTom Warren  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10*b40f734aSTom Warren  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11*b40f734aSTom Warren  * more details.
12*b40f734aSTom Warren  *
13*b40f734aSTom Warren  * You should have received a copy of the GNU General Public License
14*b40f734aSTom Warren  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15*b40f734aSTom Warren  */
16*b40f734aSTom Warren 
17*b40f734aSTom Warren #ifndef _TEGRA114_SYSCTR_H_
18*b40f734aSTom Warren #define _TEGRA114_SYSCTR_H_
19*b40f734aSTom Warren 
20*b40f734aSTom Warren struct sysctr_ctlr {
21*b40f734aSTom Warren 	u32 cntcr;		/* 0x00: SYSCTR0_CNTCR Counter Control */
22*b40f734aSTom Warren 	u32 cntsr;		/* 0x04: SYSCTR0_CNTSR Counter Status */
23*b40f734aSTom Warren 	u32 cntcv0;		/* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
24*b40f734aSTom Warren 	u32 cntcv1;		/* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
25*b40f734aSTom Warren 	u32 reserved1[4];	/* 0x10 - 0x1C */
26*b40f734aSTom Warren 	u32 cntfid0;		/* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
27*b40f734aSTom Warren 	u32 cntfid1;		/* 0x24: SYSCTR0_CNTFID1 Freq Table End */
28*b40f734aSTom Warren 	u32 reserved2[1002];	/* 0x28 - 0xFCC */
29*b40f734aSTom Warren 	u32 counterid[12];	/* 0xFD0 - 0xFxx CounterID regs, RO */
30*b40f734aSTom Warren };
31*b40f734aSTom Warren 
32*b40f734aSTom Warren #define TSC_CNTCR_ENABLE	(1 << 0)	/* Enable */
33*b40f734aSTom Warren #define TSC_CNTCR_HDBG		(1 << 1)	/* Halt on debug */
34*b40f734aSTom Warren 
35*b40f734aSTom Warren #endif	/* _TEGRA114_SYSCTR_H_ */
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