1*1c82c2f6SSimon Glass /* 2*1c82c2f6SSimon Glass * Tegra pulse width frequency modulator definitions 3*1c82c2f6SSimon Glass * 4*1c82c2f6SSimon Glass * Copyright (c) 2011 The Chromium OS Authors. 5*1c82c2f6SSimon Glass * 6*1c82c2f6SSimon Glass * SPDX-License-Identifier: GPL-2.0+ 7*1c82c2f6SSimon Glass */ 8*1c82c2f6SSimon Glass 9*1c82c2f6SSimon Glass #ifndef __ASM_ARCH_TEGRA_PWM_H 10*1c82c2f6SSimon Glass #define __ASM_ARCH_TEGRA_PWM_H 11*1c82c2f6SSimon Glass 12*1c82c2f6SSimon Glass /* This is a single PWM channel */ 13*1c82c2f6SSimon Glass struct pwm_ctlr { 14*1c82c2f6SSimon Glass uint control; /* Control register */ 15*1c82c2f6SSimon Glass uint reserved[3]; /* Space space */ 16*1c82c2f6SSimon Glass }; 17*1c82c2f6SSimon Glass 18*1c82c2f6SSimon Glass #define PWM_NUM_CHANNELS 4 19*1c82c2f6SSimon Glass 20*1c82c2f6SSimon Glass /* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */ 21*1c82c2f6SSimon Glass #define PWM_ENABLE_SHIFT 31 22*1c82c2f6SSimon Glass #define PWM_ENABLE_MASK (0x1 << PWM_ENABLE_SHIFT) 23*1c82c2f6SSimon Glass 24*1c82c2f6SSimon Glass #define PWM_WIDTH_SHIFT 16 25*1c82c2f6SSimon Glass #define PWM_WIDTH_MASK (0x7FFF << PWM_WIDTH_SHIFT) 26*1c82c2f6SSimon Glass 27*1c82c2f6SSimon Glass #define PWM_DIVIDER_SHIFT 0 28*1c82c2f6SSimon Glass #define PWM_DIVIDER_MASK (0x1FFF << PWM_DIVIDER_SHIFT) 29*1c82c2f6SSimon Glass 30*1c82c2f6SSimon Glass #endif /* __ASM_ARCH_TEGRA_PWM_H */ 31