148510c08SThierry Reding #ifndef _TEGRA_POWERGATE_H_ 248510c08SThierry Reding #define _TEGRA_POWERGATE_H_ 348510c08SThierry Reding 448510c08SThierry Reding #include <asm/arch/clock.h> 548510c08SThierry Reding 648510c08SThierry Reding enum tegra_powergate { 748510c08SThierry Reding TEGRA_POWERGATE_CPU, 848510c08SThierry Reding TEGRA_POWERGATE_3D, 948510c08SThierry Reding TEGRA_POWERGATE_VENC, 1048510c08SThierry Reding TEGRA_POWERGATE_PCIE, 1148510c08SThierry Reding TEGRA_POWERGATE_VDEC, 1248510c08SThierry Reding TEGRA_POWERGATE_L2, 1348510c08SThierry Reding TEGRA_POWERGATE_MPE, 1448510c08SThierry Reding TEGRA_POWERGATE_HEG, 1548510c08SThierry Reding TEGRA_POWERGATE_SATA, 1648510c08SThierry Reding TEGRA_POWERGATE_CPU1, 1748510c08SThierry Reding TEGRA_POWERGATE_CPU2, 1848510c08SThierry Reding TEGRA_POWERGATE_CPU3, 1948510c08SThierry Reding TEGRA_POWERGATE_CELP, 2048510c08SThierry Reding TEGRA_POWERGATE_3D1, 2148510c08SThierry Reding TEGRA_POWERGATE_CPU0, 2248510c08SThierry Reding TEGRA_POWERGATE_C0NC, 2348510c08SThierry Reding TEGRA_POWERGATE_C1NC, 2448510c08SThierry Reding TEGRA_POWERGATE_SOR, 2548510c08SThierry Reding TEGRA_POWERGATE_DIS, 2648510c08SThierry Reding TEGRA_POWERGATE_DISB, 2748510c08SThierry Reding TEGRA_POWERGATE_XUSBA, 2848510c08SThierry Reding TEGRA_POWERGATE_XUSBB, 2948510c08SThierry Reding TEGRA_POWERGATE_XUSBC, 3048510c08SThierry Reding TEGRA_POWERGATE_VIC, 3148510c08SThierry Reding TEGRA_POWERGATE_IRAM, 3248510c08SThierry Reding }; 3348510c08SThierry Reding 3448510c08SThierry Reding int tegra_powergate_sequence_power_up(enum tegra_powergate id, 3548510c08SThierry Reding enum periph_id periph); 36*91a34ed9SJan Kiszka int tegra_powergate_power_on(enum tegra_powergate id); 3748510c08SThierry Reding int tegra_powergate_power_off(enum tegra_powergate id); 3848510c08SThierry Reding 3948510c08SThierry Reding #endif 40