1 /* 2 * (C) Copyright 2010-2014 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _TEGRA_PINMUX_H_ 9 #define _TEGRA_PINMUX_H_ 10 11 #include <asm/arch/tegra.h> 12 13 /* The pullup/pulldown state of a pin group */ 14 enum pmux_pull { 15 PMUX_PULL_NORMAL = 0, 16 PMUX_PULL_DOWN, 17 PMUX_PULL_UP, 18 }; 19 20 /* Defines whether a pin group is tristated or in normal operation */ 21 enum pmux_tristate { 22 PMUX_TRI_NORMAL = 0, 23 PMUX_TRI_TRISTATE = 1, 24 }; 25 26 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC 27 enum pmux_pin_io { 28 PMUX_PIN_OUTPUT = 0, 29 PMUX_PIN_INPUT = 1, 30 PMUX_PIN_NONE, 31 }; 32 33 enum pmux_pin_lock { 34 PMUX_PIN_LOCK_DEFAULT = 0, 35 PMUX_PIN_LOCK_DISABLE, 36 PMUX_PIN_LOCK_ENABLE, 37 }; 38 39 enum pmux_pin_od { 40 PMUX_PIN_OD_DEFAULT = 0, 41 PMUX_PIN_OD_DISABLE, 42 PMUX_PIN_OD_ENABLE, 43 }; 44 45 enum pmux_pin_ioreset { 46 PMUX_PIN_IO_RESET_DEFAULT = 0, 47 PMUX_PIN_IO_RESET_DISABLE, 48 PMUX_PIN_IO_RESET_ENABLE, 49 }; 50 51 #ifdef TEGRA_PMX_HAS_RCV_SEL 52 enum pmux_pin_rcv_sel { 53 PMUX_PIN_RCV_SEL_DEFAULT = 0, 54 PMUX_PIN_RCV_SEL_NORMAL, 55 PMUX_PIN_RCV_SEL_HIGH, 56 }; 57 #endif /* TEGRA_PMX_HAS_RCV_SEL */ 58 #endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */ 59 60 /* 61 * This defines the configuration for a pin, including the function assigned, 62 * pull up/down settings and tristate settings. Having set up one of these 63 * you can call pinmux_config_pingroup() to configure a pin in one step. Also 64 * available is pinmux_config_table() to configure a list of pins. 65 */ 66 struct pingroup_config { 67 enum pmux_pingrp pingroup; /* pin group PINGRP_... */ 68 enum pmux_func func; /* function to assign FUNC_... */ 69 enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ 70 enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ 71 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC 72 enum pmux_pin_io io; /* input or output PMUX_PIN_... */ 73 enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */ 74 enum pmux_pin_od od; /* open-drain or push-pull driver */ 75 enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */ 76 #ifdef TEGRA_PMX_HAS_RCV_SEL 77 enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */ 78 /* VIL/VIH receivers */ 79 #endif 80 #endif 81 }; 82 83 /* Set the mux function for a pin group */ 84 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); 85 86 /* Set the pull up/down feature for a pin group */ 87 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); 88 89 /* Set a pin group to tristate */ 90 void pinmux_tristate_enable(enum pmux_pingrp pin); 91 92 /* Set a pin group to normal (non tristate) */ 93 void pinmux_tristate_disable(enum pmux_pingrp pin); 94 95 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC 96 /* Set a pin group as input or output */ 97 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); 98 #endif 99 100 /** 101 * Configure a list of pin groups 102 * 103 * @param config List of config items 104 * @param len Number of config items in list 105 */ 106 void pinmux_config_table(const struct pingroup_config *config, int len); 107 108 #ifdef TEGRA_PMX_HAS_PADGRPS 109 110 #define PGRP_SLWF_MIN 0 111 #define PGRP_SLWF_MAX 3 112 #define PGRP_SLWF_NONE -1 113 114 #define PGRP_SLWR_MIN 0 115 #define PGRP_SLWR_MAX 3 116 #define PGRP_SLWR_NONE -1 117 118 #define PGRP_DRVUP_MIN 0 119 #define PGRP_DRVUP_MAX 127 120 #define PGRP_DRVUP_NONE -1 121 122 #define PGRP_DRVDN_MIN 0 123 #define PGRP_DRVDN_MAX 127 124 #define PGRP_DRVDN_NONE -1 125 126 /* Defines a pin group cfg's low-power mode select */ 127 enum pgrp_lpmd { 128 PGRP_LPMD_X8 = 0, 129 PGRP_LPMD_X4, 130 PGRP_LPMD_X2, 131 PGRP_LPMD_X, 132 PGRP_LPMD_NONE = -1, 133 }; 134 135 /* Defines whether a pin group cfg's schmidt is enabled or not */ 136 enum pgrp_schmt { 137 PGRP_SCHMT_DISABLE = 0, 138 PGRP_SCHMT_ENABLE = 1, 139 PGRP_SCHMT_NONE = -1, 140 }; 141 142 /* Defines whether a pin group cfg's high-speed mode is enabled or not */ 143 enum pgrp_hsm { 144 PGRP_HSM_DISABLE = 0, 145 PGRP_HSM_ENABLE = 1, 146 PGRP_HSM_NONE = -1, 147 }; 148 149 /* 150 * This defines the configuration for a pin group's pad control config 151 */ 152 struct padctrl_config { 153 enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */ 154 int slwf; /* falling edge slew */ 155 int slwr; /* rising edge slew */ 156 int drvup; /* pull-up drive strength */ 157 int drvdn; /* pull-down drive strength */ 158 enum pgrp_lpmd lpmd; /* low-power mode selection */ 159 enum pgrp_schmt schmt; /* schmidt enable */ 160 enum pgrp_hsm hsm; /* high-speed mode enable */ 161 }; 162 163 /** 164 * Set the GP pad configs 165 * 166 * @param config List of config items 167 * @param len Number of config items in list 168 */ 169 void padgrp_config_table(const struct padctrl_config *config, int len); 170 171 #endif /* TEGRA_PMX_HAS_PADGRPS */ 172 173 struct tegra_pingroup_desc { 174 enum pmux_func funcs[4]; 175 #if defined(CONFIG_TEGRA20) 176 u32 ctl_id; 177 u32 pull_id; 178 #endif /* CONFIG_TEGRA20 */ 179 }; 180 181 extern const struct tegra_pingroup_desc *tegra_soc_pingroups; 182 183 #endif /* _TEGRA_PINMUX_H_ */ 184