1 /* 2 * (C) Copyright 2010-2014 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _TEGRA_PINMUX_H_ 9 #define _TEGRA_PINMUX_H_ 10 11 #include <asm/arch/tegra.h> 12 13 /* The pullup/pulldown state of a pin group */ 14 enum pmux_pull { 15 PMUX_PULL_NORMAL = 0, 16 PMUX_PULL_DOWN, 17 PMUX_PULL_UP, 18 }; 19 20 /* Defines whether a pin group is tristated or in normal operation */ 21 enum pmux_tristate { 22 PMUX_TRI_NORMAL = 0, 23 PMUX_TRI_TRISTATE = 1, 24 }; 25 26 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT 27 enum pmux_pin_io { 28 PMUX_PIN_OUTPUT = 0, 29 PMUX_PIN_INPUT = 1, 30 PMUX_PIN_NONE, 31 }; 32 #endif 33 34 #ifdef TEGRA_PMX_PINS_HAVE_LOCK 35 enum pmux_pin_lock { 36 PMUX_PIN_LOCK_DEFAULT = 0, 37 PMUX_PIN_LOCK_DISABLE, 38 PMUX_PIN_LOCK_ENABLE, 39 }; 40 #endif 41 42 #ifdef TEGRA_PMX_PINS_HAVE_OD 43 enum pmux_pin_od { 44 PMUX_PIN_OD_DEFAULT = 0, 45 PMUX_PIN_OD_DISABLE, 46 PMUX_PIN_OD_ENABLE, 47 }; 48 #endif 49 50 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET 51 enum pmux_pin_ioreset { 52 PMUX_PIN_IO_RESET_DEFAULT = 0, 53 PMUX_PIN_IO_RESET_DISABLE, 54 PMUX_PIN_IO_RESET_ENABLE, 55 }; 56 #endif 57 58 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL 59 enum pmux_pin_rcv_sel { 60 PMUX_PIN_RCV_SEL_DEFAULT = 0, 61 PMUX_PIN_RCV_SEL_NORMAL, 62 PMUX_PIN_RCV_SEL_HIGH, 63 }; 64 #endif 65 66 /* 67 * This defines the configuration for a pin, including the function assigned, 68 * pull up/down settings and tristate settings. Having set up one of these 69 * you can call pinmux_config_pingroup() to configure a pin in one step. Also 70 * available is pinmux_config_table() to configure a list of pins. 71 */ 72 struct pmux_pingrp_config { 73 u32 pingrp:16; /* pin group PMUX_PINGRP_... */ 74 u32 func:8; /* function to assign PMUX_FUNC_... */ 75 u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/ 76 u32 tristate:2; /* tristate or normal PMUX_TRI_... */ 77 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT 78 u32 io:2; /* input or output PMUX_PIN_... */ 79 #endif 80 #ifdef TEGRA_PMX_PINS_HAVE_LOCK 81 u32 lock:2; /* lock enable/disable PMUX_PIN... */ 82 #endif 83 #ifdef TEGRA_PMX_PINS_HAVE_OD 84 u32 od:2; /* open-drain or push-pull driver */ 85 #endif 86 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET 87 u32 ioreset:2; /* input/output reset PMUX_PIN... */ 88 #endif 89 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL 90 u32 rcv_sel:2; /* select between High and Normal */ 91 /* VIL/VIH receivers */ 92 #endif 93 }; 94 95 #ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING 96 /* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */ 97 void pinmux_set_tristate_input_clamping(void); 98 void pinmux_clear_tristate_input_clamping(void); 99 #endif 100 101 /* Set the mux function for a pin group */ 102 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); 103 104 /* Set the pull up/down feature for a pin group */ 105 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); 106 107 /* Set a pin group to tristate */ 108 void pinmux_tristate_enable(enum pmux_pingrp pin); 109 110 /* Set a pin group to normal (non tristate) */ 111 void pinmux_tristate_disable(enum pmux_pingrp pin); 112 113 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT 114 /* Set a pin group as input or output */ 115 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); 116 #endif 117 118 /** 119 * Configure a list of pin groups 120 * 121 * @param config List of config items 122 * @param len Number of config items in list 123 */ 124 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, 125 int len); 126 127 #ifdef TEGRA_PMX_SOC_HAS_DRVGRPS 128 129 #define PMUX_SLWF_MIN 0 130 #define PMUX_SLWF_MAX 3 131 #define PMUX_SLWF_NONE -1 132 133 #define PMUX_SLWR_MIN 0 134 #define PMUX_SLWR_MAX 3 135 #define PMUX_SLWR_NONE -1 136 137 #define PMUX_DRVUP_MIN 0 138 #define PMUX_DRVUP_MAX 127 139 #define PMUX_DRVUP_NONE -1 140 141 #define PMUX_DRVDN_MIN 0 142 #define PMUX_DRVDN_MAX 127 143 #define PMUX_DRVDN_NONE -1 144 145 /* Defines a pin group cfg's low-power mode select */ 146 enum pmux_lpmd { 147 PMUX_LPMD_X8 = 0, 148 PMUX_LPMD_X4, 149 PMUX_LPMD_X2, 150 PMUX_LPMD_X, 151 PMUX_LPMD_NONE = -1, 152 }; 153 154 /* Defines whether a pin group cfg's schmidt is enabled or not */ 155 enum pmux_schmt { 156 PMUX_SCHMT_DISABLE = 0, 157 PMUX_SCHMT_ENABLE = 1, 158 PMUX_SCHMT_NONE = -1, 159 }; 160 161 /* Defines whether a pin group cfg's high-speed mode is enabled or not */ 162 enum pmux_hsm { 163 PMUX_HSM_DISABLE = 0, 164 PMUX_HSM_ENABLE = 1, 165 PMUX_HSM_NONE = -1, 166 }; 167 168 /* 169 * This defines the configuration for a pin group's pad control config 170 */ 171 struct pmux_drvgrp_config { 172 u32 drvgrp:16; /* pin group PMUX_DRVGRP_x */ 173 u32 slwf:3; /* falling edge slew */ 174 u32 slwr:3; /* rising edge slew */ 175 u32 drvup:8; /* pull-up drive strength */ 176 u32 drvdn:8; /* pull-down drive strength */ 177 u32 lpmd:3; /* low-power mode selection */ 178 u32 schmt:2; /* schmidt enable */ 179 u32 hsm:2; /* high-speed mode enable */ 180 }; 181 182 /** 183 * Set the GP pad configs 184 * 185 * @param config List of config items 186 * @param len Number of config items in list 187 */ 188 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, 189 int len); 190 191 #endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ 192 193 struct pmux_pingrp_desc { 194 u8 funcs[4]; 195 #if defined(CONFIG_TEGRA20) 196 u8 ctl_id; 197 u8 pull_id; 198 #endif /* CONFIG_TEGRA20 */ 199 }; 200 201 extern const struct pmux_pingrp_desc *tegra_soc_pingroups; 202 203 #endif /* _TEGRA_PINMUX_H_ */ 204