xref: /rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra/gp_padctrl.h (revision cc35734358540a1bbaf042fdf9f4cb2de17389ed)
1dc89ad14STom Warren /*
2*7aaa5a60STom Warren  *  (C) Copyright 2010-2015
3dc89ad14STom Warren  *  NVIDIA Corporation <www.nvidia.com>
4dc89ad14STom Warren  *
51a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
6dc89ad14STom Warren  */
7dc89ad14STom Warren 
8dc89ad14STom Warren #ifndef _TEGRA_GP_PADCTRL_H_
9dc89ad14STom Warren #define _TEGRA_GP_PADCTRL_H_
10dc89ad14STom Warren 
11dc89ad14STom Warren #define GP_HIDREV			0x804
12dc89ad14STom Warren 
13dc89ad14STom Warren /* bit fields definitions for APB_MISC_GP_HIDREV register */
14dc89ad14STom Warren #define HIDREV_CHIPID_SHIFT		8
15dc89ad14STom Warren #define HIDREV_CHIPID_MASK		(0xff << HIDREV_CHIPID_SHIFT)
16dc89ad14STom Warren #define HIDREV_MAJORPREV_SHIFT		4
17dc89ad14STom Warren #define HIDREV_MAJORPREV_MASK		(0xf << HIDREV_MAJORPREV_SHIFT)
18dc89ad14STom Warren 
19dc89ad14STom Warren /* CHIPID field returned from APB_MISC_GP_HIDREV register */
20dc89ad14STom Warren #define CHIPID_TEGRA20			0x20
21dc89ad14STom Warren #define CHIPID_TEGRA30			0x30
222fc65e28STom Warren #define CHIPID_TEGRA114			0x35
23999c6bafSTom Warren #define CHIPID_TEGRA124			0x40
24*7aaa5a60STom Warren #define CHIPID_TEGRA210			0x21
25dc89ad14STom Warren 
26dc89ad14STom Warren #endif	/* _TEGRA_GP_PADCTRL_H_ */
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