1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* Tegra clock control functions */ 8 9 #ifndef _TEGRA_CLOCK_H_ 10 #define _TEGRA_CLOCK_H_ 11 12 /* Set of oscillator frequencies supported in the internal API. */ 13 enum clock_osc_freq { 14 /* All in MHz, so 13_0 is 13.0MHz */ 15 CLOCK_OSC_FREQ_13_0, 16 CLOCK_OSC_FREQ_19_2, 17 CLOCK_OSC_FREQ_12_0, 18 CLOCK_OSC_FREQ_26_0, 19 20 CLOCK_OSC_FREQ_COUNT, 21 }; 22 23 enum { 24 MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */ 25 MASK_BITS_31_29, 26 MASK_BITS_29_28, 27 }; 28 29 #include <asm/arch/clock-tables.h> 30 /* PLL stabilization delay in usec */ 31 #define CLOCK_PLL_STABLE_DELAY_US 300 32 33 /* return the current oscillator clock frequency */ 34 enum clock_osc_freq clock_get_osc_freq(void); 35 36 /** 37 * Start PLL using the provided configuration parameters. 38 * 39 * @param id clock id 40 * @param divm input divider 41 * @param divn feedback divider 42 * @param divp post divider 2^n 43 * @param cpcon charge pump setup control 44 * @param lfcon loop filter setup control 45 * 46 * @returns monotonic time in us that the PLL will be stable 47 */ 48 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, 49 u32 divp, u32 cpcon, u32 lfcon); 50 51 /** 52 * Set PLL output frequency 53 * 54 * @param clkid clock id 55 * @param pllout pll output id 56 * @param rate desired output rate 57 * 58 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider) 59 */ 60 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, 61 unsigned rate); 62 63 /** 64 * Read low-level parameters of a PLL. 65 * 66 * @param id clock id to read (note: USB is not supported) 67 * @param divm returns input divider 68 * @param divn returns feedback divider 69 * @param divp returns post divider 2^n 70 * @param cpcon returns charge pump setup control 71 * @param lfcon returns loop filter setup control 72 * 73 * @returns 0 if ok, -1 on error (invalid clock id) 74 */ 75 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, 76 u32 *divp, u32 *cpcon, u32 *lfcon); 77 78 /* 79 * Enable a clock 80 * 81 * @param id clock id 82 */ 83 void clock_enable(enum periph_id clkid); 84 85 /* 86 * Disable a clock 87 * 88 * @param id clock id 89 */ 90 void clock_disable(enum periph_id clkid); 91 92 /* 93 * Set whether a clock is enabled or disabled. 94 * 95 * @param id clock id 96 * @param enable 1 to enable, 0 to disable 97 */ 98 void clock_set_enable(enum periph_id clkid, int enable); 99 100 /** 101 * Reset a peripheral. This puts it in reset, waits for a delay, then takes 102 * it out of reset and waits for th delay again. 103 * 104 * @param periph_id peripheral to reset 105 * @param us_delay time to delay in microseconds 106 */ 107 void reset_periph(enum periph_id periph_id, int us_delay); 108 109 /** 110 * Put a peripheral into or out of reset. 111 * 112 * @param periph_id peripheral to reset 113 * @param enable 1 to put into reset, 0 to take out of reset 114 */ 115 void reset_set_enable(enum periph_id periph_id, int enable); 116 117 118 /* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */ 119 enum crc_reset_id { 120 /* Things we can hold in reset for each CPU */ 121 crc_rst_cpu = 1, 122 crc_rst_de = 1 << 4, /* What is de? */ 123 crc_rst_watchdog = 1 << 8, 124 crc_rst_debug = 1 << 12, 125 }; 126 127 /** 128 * Put parts of the CPU complex into or out of reset.\ 129 * 130 * @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3) 131 * @param which which parts of the complex to affect (OR of crc_reset_id) 132 * @param reset 1 to assert reset, 0 to de-assert 133 */ 134 void reset_cmplx_set_enable(int cpu, int which, int reset); 135 136 /** 137 * Set the source for a peripheral clock. This plus the divisor sets the 138 * clock rate. You need to look up the datasheet to see the meaning of the 139 * source parameter as it changes for each peripheral. 140 * 141 * Warning: This function is only for use pre-relocation. Please use 142 * clock_start_periph_pll() instead. 143 * 144 * @param periph_id peripheral to adjust 145 * @param source source clock (0, 1, 2 or 3) 146 */ 147 void clock_ll_set_source(enum periph_id periph_id, unsigned source); 148 149 /** 150 * Set the source and divisor for a peripheral clock. This sets the 151 * clock rate. You need to look up the datasheet to see the meaning of the 152 * source parameter as it changes for each peripheral. 153 * 154 * Warning: This function is only for use pre-relocation. Please use 155 * clock_start_periph_pll() instead. 156 * 157 * @param periph_id peripheral to adjust 158 * @param source source clock (0, 1, 2 or 3) 159 * @param divisor divisor value to use 160 */ 161 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, 162 unsigned divisor); 163 164 /** 165 * Start a peripheral PLL clock at the given rate. This also resets the 166 * peripheral. 167 * 168 * @param periph_id peripheral to start 169 * @param parent PLL id of required parent clock 170 * @param rate Required clock rate in Hz 171 * @return rate selected in Hz, or -1U if something went wrong 172 */ 173 unsigned clock_start_periph_pll(enum periph_id periph_id, 174 enum clock_id parent, unsigned rate); 175 176 /** 177 * Returns the rate of a peripheral clock in Hz. Since the caller almost 178 * certainly knows the parent clock (having just set it) we require that 179 * this be passed in so we don't need to work it out. 180 * 181 * @param periph_id peripheral to start 182 * @param parent PLL id of parent clock (used to calculate rate, you 183 * must know this!) 184 * @return clock rate of peripheral in Hz 185 */ 186 unsigned long clock_get_periph_rate(enum periph_id periph_id, 187 enum clock_id parent); 188 189 /** 190 * Adjust peripheral PLL clock to the given rate. This does not reset the 191 * peripheral. If a second stage divisor is not available, pass NULL for 192 * extra_div. If it is available, then this parameter will return the 193 * divisor selected (which will be a power of 2 from 1 to 256). 194 * 195 * @param periph_id peripheral to start 196 * @param parent PLL id of required parent clock 197 * @param rate Required clock rate in Hz 198 * @param extra_div value for the second-stage divisor (NULL if one is 199 not available) 200 * @return rate selected in Hz, or -1U if something went wrong 201 */ 202 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, 203 enum clock_id parent, unsigned rate, int *extra_div); 204 205 /** 206 * Returns the clock rate of a specified clock, in Hz. 207 * 208 * @param parent PLL id of clock to check 209 * @return rate of clock in Hz 210 */ 211 unsigned clock_get_rate(enum clock_id clkid); 212 213 /** 214 * Start up a UART using low-level calls 215 * 216 * Prior to relocation clock_start_periph_pll() cannot be called. This 217 * function provides a way to set up a UART using low-level calls which 218 * do not require BSS. 219 * 220 * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1) 221 */ 222 void clock_ll_start_uart(enum periph_id periph_id); 223 224 /** 225 * Decode a peripheral ID from a device tree node. 226 * 227 * This works by looking up the peripheral's 'clocks' node and reading out 228 * the second cell, which is the clock number / peripheral ID. 229 * 230 * @param blob FDT blob to use 231 * @param node Node to look at 232 * @return peripheral ID, or PERIPH_ID_NONE if none 233 */ 234 enum periph_id clock_decode_periph_id(const void *blob, int node); 235 236 /** 237 * Checks if the oscillator bypass is enabled (XOBP bit) 238 * 239 * @return 1 if bypass is enabled, 0 if not 240 */ 241 int clock_get_osc_bypass(void); 242 243 /* 244 * Checks that clocks are valid and prints a warning if not 245 * 246 * @return 0 if ok, -1 on error 247 */ 248 int clock_verify(void); 249 250 /* Initialize the clocks */ 251 void clock_init(void); 252 253 /* Initialize the PLLs */ 254 void clock_early_init(void); 255 256 /* Returns a pointer to the clock source register for a peripheral */ 257 u32 *get_periph_source_reg(enum periph_id periph_id); 258 259 /** 260 * Given a peripheral ID and the required source clock, this returns which 261 * value should be programmed into the source mux for that peripheral. 262 * 263 * There is special code here to handle the one source type with 5 sources. 264 * 265 * @param periph_id peripheral to start 266 * @param source PLL id of required parent clock 267 * @param mux_bits Set to number of bits in mux register: 2 or 4 268 * @param divider_bits Set to number of divider bits (8 or 16) 269 * @return mux value (0-4, or -1 if not found) 270 */ 271 int get_periph_clock_source(enum periph_id periph_id, 272 enum clock_id parent, int *mux_bits, int *divider_bits); 273 274 /* 275 * Convert a device tree clock ID to our peripheral ID. They are mostly 276 * the same but we are very cautious so we check that a valid clock ID is 277 * provided. 278 * 279 * @param clk_id Clock ID according to tegra30 device tree binding 280 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid 281 */ 282 enum periph_id clk_id_to_periph_id(int clk_id); 283 284 /** 285 * Set the output frequency you want for each PLL clock. 286 * PLL output frequencies are programmed by setting their N, M and P values. 287 * The governing equations are: 288 * VCO = (Fi / m) * n, Fo = VCO / (2^p) 289 * where Fo is the output frequency from the PLL. 290 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi) 291 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1 292 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming 293 * 294 * @param n PLL feedback divider(DIVN) 295 * @param m PLL input divider(DIVN) 296 * @param p post divider(DIVP) 297 * @param cpcon base PLL charge pump(CPCON) 298 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot 299 * be overriden), 1 if PLL is already correct 300 */ 301 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon); 302 303 /* return 1 if a peripheral ID is in range */ 304 #define clock_type_id_isvalid(id) ((id) >= 0 && \ 305 (id) < CLOCK_TYPE_COUNT) 306 307 /* return 1 if a periphc_internal_id is in range */ 308 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \ 309 (id) < PERIPHC_COUNT) 310 311 /* SoC-specific TSC init */ 312 void arch_timer_init(void); 313 314 #endif /* _TEGRA_CLOCK_H_ */ 315