1*19ed7b4eSStephen Warren /* 2*19ed7b4eSStephen Warren * Copyright (c) 2012 The Chromium OS Authors. 3*19ed7b4eSStephen Warren * 4*19ed7b4eSStephen Warren * SPDX-License-Identifier: GPL-2.0+ 5*19ed7b4eSStephen Warren */ 6*19ed7b4eSStephen Warren 7*19ed7b4eSStephen Warren #ifndef _GP_PADCTRL_H_ 8*19ed7b4eSStephen Warren #define _GP_PADCTRL_H_ 9*19ed7b4eSStephen Warren 10*19ed7b4eSStephen Warren /* APB_MISC_PP registers */ 11*19ed7b4eSStephen Warren struct apb_misc_pp_ctlr { 12*19ed7b4eSStephen Warren u32 reserved0[2]; 13*19ed7b4eSStephen Warren u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */ 14*19ed7b4eSStephen Warren u32 reserved1[6]; /* 0x0c .. 0x20 */ 15*19ed7b4eSStephen Warren u32 cfg_ctl; /* 0x24 */ 16*19ed7b4eSStephen Warren }; 17*19ed7b4eSStephen Warren 18*19ed7b4eSStephen Warren /* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */ 19*19ed7b4eSStephen Warren #define RAM_CODE_SHIFT 4 20*19ed7b4eSStephen Warren #define RAM_CODE_MASK (0xf << RAM_CODE_SHIFT) 21*19ed7b4eSStephen Warren 22*19ed7b4eSStephen Warren #endif 23