1643cf0eaSIan Campbell /* 2643cf0eaSIan Campbell * (C) Copyright 2007-2011 3643cf0eaSIan Campbell * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 4643cf0eaSIan Campbell * Tom Cubie <tangliang@allwinnertech.com> 5643cf0eaSIan Campbell * 6643cf0eaSIan Campbell * SPDX-License-Identifier: GPL-2.0+ 7643cf0eaSIan Campbell */ 8643cf0eaSIan Campbell 9643cf0eaSIan Campbell #ifndef _SUNXI_CLOCK_H 10643cf0eaSIan Campbell #define _SUNXI_CLOCK_H 11643cf0eaSIan Campbell 12643cf0eaSIan Campbell #include <linux/types.h> 13643cf0eaSIan Campbell 14643cf0eaSIan Campbell #define CLK_GATE_OPEN 0x1 15643cf0eaSIan Campbell #define CLK_GATE_CLOSE 0x0 16643cf0eaSIan Campbell 17643cf0eaSIan Campbell /* clock control module regs definition */ 18ed41e62fSIan Campbell #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) 1914177e47SChen-Yu Tsai #include <asm/arch/clock_sun6i.h> 2014177e47SChen-Yu Tsai #else 21643cf0eaSIan Campbell #include <asm/arch/clock_sun4i.h> 2214177e47SChen-Yu Tsai #endif 23643cf0eaSIan Campbell 24643cf0eaSIan Campbell #ifndef __ASSEMBLY__ 25643cf0eaSIan Campbell int clock_init(void); 26643cf0eaSIan Campbell int clock_twi_onoff(int port, int state); 27643cf0eaSIan Campbell void clock_set_pll1(unsigned int hz); 28*0bd51251SHans de Goede void clock_set_pll3(unsigned int hz); 2962c87ef2SHans de Goede void clock_set_pll5(unsigned int hz); 309e54f6eeSHans de Goede unsigned int clock_get_pll5p(void); 31643cf0eaSIan Campbell unsigned int clock_get_pll6(void); 32*0bd51251SHans de Goede void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz); 33643cf0eaSIan Campbell void clock_init_safe(void); 34643cf0eaSIan Campbell void clock_init_uart(void); 35643cf0eaSIan Campbell #endif 36643cf0eaSIan Campbell 37643cf0eaSIan Campbell #endif /* _SUNXI_CLOCK_H */ 38