1 /* 2 * (C) Copyright 2016 3 * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _STM32_RCC_H 9 #define _STM32_RCC_H 10 11 #define RCC_CR 0x00 /* clock control */ 12 #define RCC_PLLCFGR 0x04 /* PLL configuration */ 13 #define RCC_CFGR 0x08 /* clock configuration */ 14 #define RCC_CIR 0x0C /* clock interrupt */ 15 #define RCC_AHB1RSTR 0x10 /* AHB1 peripheral reset */ 16 #define RCC_AHB2RSTR 0x14 /* AHB2 peripheral reset */ 17 #define RCC_AHB3RSTR 0x18 /* AHB3 peripheral reset */ 18 #define RCC_APB1RSTR 0x20 /* APB1 peripheral reset */ 19 #define RCC_APB2RSTR 0x24 /* APB2 peripheral reset */ 20 #define RCC_AHB1ENR 0x30 /* AHB1 peripheral clock enable */ 21 #define RCC_AHB2ENR 0x34 /* AHB2 peripheral clock enable */ 22 #define RCC_AHB3ENR 0x38 /* AHB3 peripheral clock enable */ 23 #define RCC_APB1ENR 0x40 /* APB1 peripheral clock enable */ 24 #define RCC_APB2ENR 0x44 /* APB2 peripheral clock enable */ 25 #define RCC_AHB1LPENR 0x50 /* periph clk enable in low pwr mode */ 26 #define RCC_AHB2LPENR 0x54 /* AHB2 periph clk enable in low pwr mode */ 27 #define RCC_AHB3LPENR 0x58 /* AHB3 periph clk enable in low pwr mode */ 28 #define RCC_APB1LPENR 0x60 /* APB1 periph clk enable in low pwr mode */ 29 #define RCC_APB2LPENR 0x64 /* APB2 periph clk enable in low pwr mode */ 30 #define RCC_BDCR 0x70 /* Backup domain control */ 31 #define RCC_CSR 0x74 /* clock control & status */ 32 #define RCC_SSCGR 0x80 /* spread spectrum clock generation */ 33 #define RCC_PLLI2SCFGR 0x84 /* PLLI2S configuration */ 34 #define RCC_PLLSAICFG 0x88 /* PLLSAI configuration */ 35 #define RCC_DCKCFG1 0x8C /* dedicated clocks configuration register */ 36 #define RCC_DCKCFG2 0x90 /* dedicated clocks configuration register */ 37 /* 38 * RCC AHB1ENR specific definitions 39 */ 40 #define RCC_AHB1ENR_GPIO_A_EN BIT(0) 41 #define RCC_AHB1ENR_GPIO_B_EN BIT(1) 42 #define RCC_AHB1ENR_GPIO_C_EN BIT(2) 43 #define RCC_AHB1ENR_GPIO_D_EN BIT(3) 44 #define RCC_AHB1ENR_GPIO_E_EN BIT(4) 45 #define RCC_AHB1ENR_GPIO_F_EN BIT(5) 46 #define RCC_AHB1ENR_GPIO_G_EN BIT(6) 47 #define RCC_AHB1ENR_GPIO_H_EN BIT(7) 48 #define RCC_AHB1ENR_GPIO_I_EN BIT(8) 49 #define RCC_AHB1ENR_GPIO_J_EN BIT(9) 50 #define RCC_AHB1ENR_GPIO_K_EN BIT(10) 51 #define RCC_AHB1ENR_ETHMAC_EN BIT(25) 52 #define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26) 53 #define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27) 54 #define RCC_AHB1ENR_ETHMAC_PTP_EN BIT(28) 55 56 /* 57 * RCC AHB3ENR specific definitions 58 */ 59 #define RCC_AHB3ENR_FMC_EN BIT(0) 60 61 /* 62 * RCC APB1ENR specific definitions 63 */ 64 #define RCC_APB1ENR_TIM2EN BIT(0) 65 #define RCC_APB1ENR_USART2EN BIT(17) 66 #define RCC_APB1ENR_USART3EN BIT(18) 67 #define RCC_APB1ENR_PWREN BIT(28) 68 69 /* 70 * RCC APB2ENR specific definitions 71 */ 72 #define RCC_APB2ENR_USART1EN BIT(4) 73 #define RCC_APB2ENR_USART6EN BIT(5) 74 #define RCC_APB2ENR_SYSCFGEN BIT(14) 75 76 #endif 77