xref: /rk3399_rockchip-uboot/arch/arm/include/asm/arch-stm32f7/rcc.h (revision 4db98d3d92827e38d0853f0c1932d3db7d757622)
1 /*
2  * (C) Copyright 2016
3  * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef _STM32_RCC_H
9 #define _STM32_RCC_H
10 
11 /*
12  * RCC AHB1ENR specific definitions
13  */
14 #define RCC_AHB1ENR_GPIO_A_EN		BIT(0)
15 #define RCC_AHB1ENR_GPIO_B_EN		BIT(1)
16 #define RCC_AHB1ENR_GPIO_C_EN		BIT(2)
17 #define RCC_AHB1ENR_GPIO_D_EN		BIT(3)
18 #define RCC_AHB1ENR_GPIO_E_EN		BIT(4)
19 #define RCC_AHB1ENR_GPIO_F_EN		BIT(5)
20 #define RCC_AHB1ENR_GPIO_G_EN		BIT(6)
21 #define RCC_AHB1ENR_GPIO_H_EN		BIT(7)
22 #define RCC_AHB1ENR_GPIO_I_EN		BIT(8)
23 #define RCC_AHB1ENR_GPIO_J_EN		BIT(9)
24 #define RCC_AHB1ENR_GPIO_K_EN		BIT(10)
25 #define RCC_AHB1ENR_ETHMAC_EN		BIT(25)
26 #define RCC_AHB1ENR_ETHMAC_TX_EN	BIT(26)
27 #define RCC_AHB1ENR_ETHMAC_RX_EN	BIT(27)
28 #define RCC_AHB1ENR_ETHMAC_PTP_EN	BIT(28)
29 
30 /*
31  * RCC AHB3ENR specific definitions
32  */
33 #define RCC_AHB3ENR_FMC_EN		BIT(0)
34 #define RCC_AHB3ENR_QSPI_EN             BIT(1)
35 
36 /*
37  * RCC APB1ENR specific definitions
38  */
39 #define RCC_APB1ENR_TIM2EN		BIT(0)
40 #define RCC_APB1ENR_USART2EN		BIT(17)
41 #define RCC_APB1ENR_USART3EN		BIT(18)
42 #define RCC_APB1ENR_PWREN		BIT(28)
43 
44 /*
45  * RCC APB2ENR specific definitions
46  */
47 #define RCC_APB2ENR_USART1EN		BIT(4)
48 #define RCC_APB2ENR_USART6EN		BIT(5)
49 #define RCC_APB2ENR_SYSCFGEN		BIT(14)
50 
51 #endif
52