1*eee20f81SPatrice Chotard /* 2*eee20f81SPatrice Chotard * (C) Copyright 2017 Patrice Chotard <patrice.chotard@st.com> 3*eee20f81SPatrice Chotard * 4*eee20f81SPatrice Chotard * SPDX-License-Identifier: GPL-2.0+ 5*eee20f81SPatrice Chotard */ 6*eee20f81SPatrice Chotard 7*eee20f81SPatrice Chotard #ifndef __STI_SDHCI_H__ 8*eee20f81SPatrice Chotard #define __STI_SDHCI_H__ 9*eee20f81SPatrice Chotard 10*eee20f81SPatrice Chotard #define FLASHSS_MMC_CORE_CONFIG_1 0x400 11*eee20f81SPatrice Chotard #define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ BIT(24) 12*eee20f81SPatrice Chotard #define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN BIT(12) 13*eee20f81SPatrice Chotard 14*eee20f81SPatrice Chotard #define STI_FLASHSS_MMC_CORE_CONFIG_1 \ 15*eee20f81SPatrice Chotard (FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ | \ 16*eee20f81SPatrice Chotard FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN) 17*eee20f81SPatrice Chotard 18*eee20f81SPatrice Chotard #define FLASHSS_MMC_CORE_CONFIG_2 0x404 19*eee20f81SPatrice Chotard #define FLASHSS_MMC_CORECFG_HIGH_SPEED BIT(28) 20*eee20f81SPatrice Chotard #define FLASHSS_MMC_CORECFG_8BIT_EMMC BIT(20) 21*eee20f81SPatrice Chotard #define MAX_BLK_LENGTH_1024 BIT(16) 22*eee20f81SPatrice Chotard #define BASE_CLK_FREQ_200 0xc8 23*eee20f81SPatrice Chotard 24*eee20f81SPatrice Chotard #define STI_FLASHSS_MMC_CORE_CONFIG2 \ 25*eee20f81SPatrice Chotard (FLASHSS_MMC_CORECFG_HIGH_SPEED | \ 26*eee20f81SPatrice Chotard FLASHSS_MMC_CORECFG_8BIT_EMMC | \ 27*eee20f81SPatrice Chotard MAX_BLK_LENGTH_1024 | \ 28*eee20f81SPatrice Chotard BASE_CLK_FREQ_200 << 0) 29*eee20f81SPatrice Chotard 30*eee20f81SPatrice Chotard #define STI_FLASHSS_SDCARD_CORE_CONFIG2 \ 31*eee20f81SPatrice Chotard (FLASHSS_MMC_CORECFG_HIGH_SPEED | \ 32*eee20f81SPatrice Chotard MAX_BLK_LENGTH_1024 | \ 33*eee20f81SPatrice Chotard BASE_CLK_FREQ_200) 34*eee20f81SPatrice Chotard 35*eee20f81SPatrice Chotard #define FLASHSS_MMC_CORE_CONFIG_3 0x408 36*eee20f81SPatrice Chotard #define FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC BIT(28) 37*eee20f81SPatrice Chotard #define FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT BIT(20) 38*eee20f81SPatrice Chotard #define FLASHSS_MMC_CORECFG_3P3_VOLT BIT(8) 39*eee20f81SPatrice Chotard #define FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT BIT(4) 40*eee20f81SPatrice Chotard #define FLASHSS_MMC_CORECFG_SDMA BIT(0) 41*eee20f81SPatrice Chotard 42*eee20f81SPatrice Chotard #define STI_FLASHSS_MMC_CORE_CONFIG3 \ 43*eee20f81SPatrice Chotard (FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC | \ 44*eee20f81SPatrice Chotard FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \ 45*eee20f81SPatrice Chotard FLASHSS_MMC_CORECFG_3P3_VOLT | \ 46*eee20f81SPatrice Chotard FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \ 47*eee20f81SPatrice Chotard FLASHSS_MMC_CORECFG_SDMA) 48*eee20f81SPatrice Chotard 49*eee20f81SPatrice Chotard #define STI_FLASHSS_SDCARD_CORE_CONFIG3 \ 50*eee20f81SPatrice Chotard (FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \ 51*eee20f81SPatrice Chotard FLASHSS_MMC_CORECFG_3P3_VOLT | \ 52*eee20f81SPatrice Chotard FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \ 53*eee20f81SPatrice Chotard FLASHSS_MMC_CORECFG_SDMA) 54*eee20f81SPatrice Chotard 55*eee20f81SPatrice Chotard #define FLASHSS_MMC_CORE_CONFIG_4 0x40c 56*eee20f81SPatrice Chotard #define FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT BIT(20) 57*eee20f81SPatrice Chotard #define FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT BIT(16) 58*eee20f81SPatrice Chotard #define FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT BIT(12) 59*eee20f81SPatrice Chotard 60*eee20f81SPatrice Chotard #define STI_FLASHSS_MMC_CORE_CONFIG4 \ 61*eee20f81SPatrice Chotard (FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT | \ 62*eee20f81SPatrice Chotard FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT | \ 63*eee20f81SPatrice Chotard FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT) 64*eee20f81SPatrice Chotard 65*eee20f81SPatrice Chotard #define ST_MMC_CCONFIG_REG_5 0x210 66*eee20f81SPatrice Chotard #define SYSCONF_MMC1_ENABLE_BIT 3 67*eee20f81SPatrice Chotard 68*eee20f81SPatrice Chotard #endif /* _STI_SDHCI_H_ */ 69