1*9702ec00SEddy Petrișor /* 2*9702ec00SEddy Petrișor * (C) Copyright 2015, Freescale Semiconductor, Inc. 3*9702ec00SEddy Petrișor * 4*9702ec00SEddy Petrișor * SPDX-License-Identifier: GPL-2.0+ 5*9702ec00SEddy Petrișor */ 6*9702ec00SEddy Petrișor 7*9702ec00SEddy Petrișor #ifndef __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ 8*9702ec00SEddy Petrișor #define __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ 9*9702ec00SEddy Petrișor 10*9702ec00SEddy Petrișor #define MC_RGM_DES (MC_RGM_BASE_ADDR) 11*9702ec00SEddy Petrișor #define MC_RGM_FES (MC_RGM_BASE_ADDR + 0x300) 12*9702ec00SEddy Petrișor #define MC_RGM_FERD (MC_RGM_BASE_ADDR + 0x310) 13*9702ec00SEddy Petrișor #define MC_RGM_FBRE (MC_RGM_BASE_ADDR + 0x330) 14*9702ec00SEddy Petrișor #define MC_RGM_FESS (MC_RGM_BASE_ADDR + 0x340) 15*9702ec00SEddy Petrișor #define MC_RGM_DDR_HE (MC_RGM_BASE_ADDR + 0x350) 16*9702ec00SEddy Petrișor #define MC_RGM_DDR_HS (MC_RGM_BASE_ADDR + 0x354) 17*9702ec00SEddy Petrișor #define MC_RGM_FRHE (MC_RGM_BASE_ADDR + 0x358) 18*9702ec00SEddy Petrișor #define MC_RGM_FREC (MC_RGM_BASE_ADDR + 0x600) 19*9702ec00SEddy Petrișor #define MC_RGM_FRET (MC_RGM_BASE_ADDR + 0x607) 20*9702ec00SEddy Petrișor #define MC_RGM_DRET (MC_RGM_BASE_ADDR + 0x60B) 21*9702ec00SEddy Petrișor 22*9702ec00SEddy Petrișor /* function reset sources mask */ 23*9702ec00SEddy Petrișor #define F_SWT4 0x8000 24*9702ec00SEddy Petrișor #define F_JTAG 0x400 25*9702ec00SEddy Petrișor #define F_FCCU_SOFT 0x40 26*9702ec00SEddy Petrișor #define F_FCCU_HARD 0x20 27*9702ec00SEddy Petrișor #define F_SOFT_FUNC 0x8 28*9702ec00SEddy Petrișor #define F_ST_DONE 0x4 29*9702ec00SEddy Petrișor #define F_EXT_RST 0x1 30*9702ec00SEddy Petrișor 31*9702ec00SEddy Petrișor #endif /* __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ */ 32