1*9702ec00SEddy Petrișor /* 2*9702ec00SEddy Petrișor * (C) Copyright 2015-2016, Freescale Semiconductor, Inc. 3*9702ec00SEddy Petrișor * 4*9702ec00SEddy Petrișor * SPDX-License-Identifier: GPL-2.0+ 5*9702ec00SEddy Petrișor */ 6*9702ec00SEddy Petrișor 7*9702ec00SEddy Petrișor #ifndef __ARCH_ARM_MACH_S32V234_DDR_H__ 8*9702ec00SEddy Petrișor #define __ARCH_ARM_MACH_S32V234_DDR_H__ 9*9702ec00SEddy Petrișor 10*9702ec00SEddy Petrișor #define DDR0 0 11*9702ec00SEddy Petrișor #define DDR1 1 12*9702ec00SEddy Petrișor 13*9702ec00SEddy Petrișor /* DDR offset in MSCR register */ 14*9702ec00SEddy Petrișor #define _DDR0_RESET 168 15*9702ec00SEddy Petrișor #define _DDR0_CLK0 169 16*9702ec00SEddy Petrișor #define _DDR0_CAS 170 17*9702ec00SEddy Petrișor #define _DDR0_RAS 171 18*9702ec00SEddy Petrișor #define _DDR0_WE_B 172 19*9702ec00SEddy Petrișor #define _DDR0_CKE0 173 20*9702ec00SEddy Petrișor #define _DDR0_CKE1 174 21*9702ec00SEddy Petrișor #define _DDR0_CS_B0 175 22*9702ec00SEddy Petrișor #define _DDR0_CS_B1 176 23*9702ec00SEddy Petrișor #define _DDR0_BA0 177 24*9702ec00SEddy Petrișor #define _DDR0_BA1 178 25*9702ec00SEddy Petrișor #define _DDR0_BA2 179 26*9702ec00SEddy Petrișor #define _DDR0_A0 180 27*9702ec00SEddy Petrișor #define _DDR0_A1 181 28*9702ec00SEddy Petrișor #define _DDR0_A2 182 29*9702ec00SEddy Petrișor #define _DDR0_A3 183 30*9702ec00SEddy Petrișor #define _DDR0_A4 184 31*9702ec00SEddy Petrișor #define _DDR0_A5 185 32*9702ec00SEddy Petrișor #define _DDR0_A6 186 33*9702ec00SEddy Petrișor #define _DDR0_A7 187 34*9702ec00SEddy Petrișor #define _DDR0_A8 188 35*9702ec00SEddy Petrișor #define _DDR0_A9 189 36*9702ec00SEddy Petrișor #define _DDR0_A10 190 37*9702ec00SEddy Petrișor #define _DDR0_A11 191 38*9702ec00SEddy Petrișor #define _DDR0_A12 192 39*9702ec00SEddy Petrișor #define _DDR0_A13 193 40*9702ec00SEddy Petrișor #define _DDR0_A14 194 41*9702ec00SEddy Petrișor #define _DDR0_A15 195 42*9702ec00SEddy Petrișor #define _DDR0_DM0 196 43*9702ec00SEddy Petrișor #define _DDR0_DM1 197 44*9702ec00SEddy Petrișor #define _DDR0_DM2 198 45*9702ec00SEddy Petrișor #define _DDR0_DM3 199 46*9702ec00SEddy Petrișor #define _DDR0_DQS0 200 47*9702ec00SEddy Petrișor #define _DDR0_DQS1 201 48*9702ec00SEddy Petrișor #define _DDR0_DQS2 202 49*9702ec00SEddy Petrișor #define _DDR0_DQS3 203 50*9702ec00SEddy Petrișor #define _DDR0_D0 204 51*9702ec00SEddy Petrișor #define _DDR0_D1 205 52*9702ec00SEddy Petrișor #define _DDR0_D2 206 53*9702ec00SEddy Petrișor #define _DDR0_D3 207 54*9702ec00SEddy Petrișor #define _DDR0_D4 208 55*9702ec00SEddy Petrișor #define _DDR0_D5 209 56*9702ec00SEddy Petrișor #define _DDR0_D6 210 57*9702ec00SEddy Petrișor #define _DDR0_D7 211 58*9702ec00SEddy Petrișor #define _DDR0_D8 212 59*9702ec00SEddy Petrișor #define _DDR0_D9 213 60*9702ec00SEddy Petrișor #define _DDR0_D10 214 61*9702ec00SEddy Petrișor #define _DDR0_D11 215 62*9702ec00SEddy Petrișor #define _DDR0_D12 216 63*9702ec00SEddy Petrișor #define _DDR0_D13 217 64*9702ec00SEddy Petrișor #define _DDR0_D14 218 65*9702ec00SEddy Petrișor #define _DDR0_D15 219 66*9702ec00SEddy Petrișor #define _DDR0_D16 220 67*9702ec00SEddy Petrișor #define _DDR0_D17 221 68*9702ec00SEddy Petrișor #define _DDR0_D18 222 69*9702ec00SEddy Petrișor #define _DDR0_D19 223 70*9702ec00SEddy Petrișor #define _DDR0_D20 224 71*9702ec00SEddy Petrișor #define _DDR0_D21 225 72*9702ec00SEddy Petrișor #define _DDR0_D22 226 73*9702ec00SEddy Petrișor #define _DDR0_D23 227 74*9702ec00SEddy Petrișor #define _DDR0_D24 228 75*9702ec00SEddy Petrișor #define _DDR0_D25 229 76*9702ec00SEddy Petrișor #define _DDR0_D26 230 77*9702ec00SEddy Petrișor #define _DDR0_D27 231 78*9702ec00SEddy Petrișor #define _DDR0_D28 232 79*9702ec00SEddy Petrișor #define _DDR0_D29 233 80*9702ec00SEddy Petrișor #define _DDR0_D30 234 81*9702ec00SEddy Petrișor #define _DDR0_D31 235 82*9702ec00SEddy Petrișor #define _DDR0_ODT0 236 83*9702ec00SEddy Petrișor #define _DDR0_ODT1 237 84*9702ec00SEddy Petrișor #define _DDR0_ZQ 238 85*9702ec00SEddy Petrișor #define _DDR1_RESET 239 86*9702ec00SEddy Petrișor #define _DDR1_CLK0 240 87*9702ec00SEddy Petrișor #define _DDR1_CAS 241 88*9702ec00SEddy Petrișor #define _DDR1_RAS 242 89*9702ec00SEddy Petrișor #define _DDR1_WE_B 243 90*9702ec00SEddy Petrișor #define _DDR1_CKE0 244 91*9702ec00SEddy Petrișor #define _DDR1_CKE1 245 92*9702ec00SEddy Petrișor #define _DDR1_CS_B0 246 93*9702ec00SEddy Petrișor #define _DDR1_CS_B1 247 94*9702ec00SEddy Petrișor #define _DDR1_BA0 248 95*9702ec00SEddy Petrișor #define _DDR1_BA1 249 96*9702ec00SEddy Petrișor #define _DDR1_BA2 250 97*9702ec00SEddy Petrișor #define _DDR1_A0 251 98*9702ec00SEddy Petrișor #define _DDR1_A1 252 99*9702ec00SEddy Petrișor #define _DDR1_A2 253 100*9702ec00SEddy Petrișor #define _DDR1_A3 254 101*9702ec00SEddy Petrișor #define _DDR1_A4 255 102*9702ec00SEddy Petrișor #define _DDR1_A5 256 103*9702ec00SEddy Petrișor #define _DDR1_A6 257 104*9702ec00SEddy Petrișor #define _DDR1_A7 258 105*9702ec00SEddy Petrișor #define _DDR1_A8 259 106*9702ec00SEddy Petrișor #define _DDR1_A9 260 107*9702ec00SEddy Petrișor #define _DDR1_A10 261 108*9702ec00SEddy Petrișor #define _DDR1_A11 262 109*9702ec00SEddy Petrișor #define _DDR1_A12 263 110*9702ec00SEddy Petrișor #define _DDR1_A13 264 111*9702ec00SEddy Petrișor #define _DDR1_A14 265 112*9702ec00SEddy Petrișor #define _DDR1_A15 266 113*9702ec00SEddy Petrișor #define _DDR1_DM0 267 114*9702ec00SEddy Petrișor #define _DDR1_DM1 268 115*9702ec00SEddy Petrișor #define _DDR1_DM2 269 116*9702ec00SEddy Petrișor #define _DDR1_DM3 270 117*9702ec00SEddy Petrișor #define _DDR1_DQS0 271 118*9702ec00SEddy Petrișor #define _DDR1_DQS1 272 119*9702ec00SEddy Petrișor #define _DDR1_DQS2 273 120*9702ec00SEddy Petrișor #define _DDR1_DQS3 274 121*9702ec00SEddy Petrișor #define _DDR1_D0 275 122*9702ec00SEddy Petrișor #define _DDR1_D1 276 123*9702ec00SEddy Petrișor #define _DDR1_D2 277 124*9702ec00SEddy Petrișor #define _DDR1_D3 278 125*9702ec00SEddy Petrișor #define _DDR1_D4 279 126*9702ec00SEddy Petrișor #define _DDR1_D5 280 127*9702ec00SEddy Petrișor #define _DDR1_D6 281 128*9702ec00SEddy Petrișor #define _DDR1_D7 282 129*9702ec00SEddy Petrișor #define _DDR1_D8 283 130*9702ec00SEddy Petrișor #define _DDR1_D9 284 131*9702ec00SEddy Petrișor #define _DDR1_D10 285 132*9702ec00SEddy Petrișor #define _DDR1_D11 286 133*9702ec00SEddy Petrișor #define _DDR1_D12 287 134*9702ec00SEddy Petrișor #define _DDR1_D13 288 135*9702ec00SEddy Petrișor #define _DDR1_D14 289 136*9702ec00SEddy Petrișor #define _DDR1_D15 290 137*9702ec00SEddy Petrișor #define _DDR1_D16 291 138*9702ec00SEddy Petrișor #define _DDR1_D17 292 139*9702ec00SEddy Petrișor #define _DDR1_D18 293 140*9702ec00SEddy Petrișor #define _DDR1_D19 294 141*9702ec00SEddy Petrișor #define _DDR1_D20 295 142*9702ec00SEddy Petrișor #define _DDR1_D21 296 143*9702ec00SEddy Petrișor #define _DDR1_D22 297 144*9702ec00SEddy Petrișor #define _DDR1_D23 298 145*9702ec00SEddy Petrișor #define _DDR1_D24 299 146*9702ec00SEddy Petrișor #define _DDR1_D25 300 147*9702ec00SEddy Petrișor #define _DDR1_D26 301 148*9702ec00SEddy Petrișor #define _DDR1_D27 302 149*9702ec00SEddy Petrișor #define _DDR1_D28 303 150*9702ec00SEddy Petrișor #define _DDR1_D29 304 151*9702ec00SEddy Petrișor #define _DDR1_D30 305 152*9702ec00SEddy Petrișor #define _DDR1_D31 306 153*9702ec00SEddy Petrișor #define _DDR1_ODT0 307 154*9702ec00SEddy Petrișor #define _DDR1_ODT1 308 155*9702ec00SEddy Petrișor #define _DDR1_ZQ 309 156*9702ec00SEddy Petrișor 157*9702ec00SEddy Petrișor #endif 158