xref: /rk3399_rockchip-uboot/arch/arm/include/asm/arch-s32v234/clock.h (revision 9702ec00e95dbc1fd66ef8e9624c649e1ee818e5)
1*9702ec00SEddy Petrișor /*
2*9702ec00SEddy Petrișor  * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
3*9702ec00SEddy Petrișor  *
4*9702ec00SEddy Petrișor  * SPDX-License-Identifier:	GPL-2.0+
5*9702ec00SEddy Petrișor  */
6*9702ec00SEddy Petrișor 
7*9702ec00SEddy Petrișor #ifndef __ASM_ARCH_CLOCK_H
8*9702ec00SEddy Petrișor #define __ASM_ARCH_CLOCK_H
9*9702ec00SEddy Petrișor 
10*9702ec00SEddy Petrișor #include <common.h>
11*9702ec00SEddy Petrișor 
12*9702ec00SEddy Petrișor enum mxc_clock {
13*9702ec00SEddy Petrișor 	MXC_ARM_CLK = 0,
14*9702ec00SEddy Petrișor 	MXC_BUS_CLK,
15*9702ec00SEddy Petrișor 	MXC_PERIPHERALS_CLK,
16*9702ec00SEddy Petrișor 	MXC_UART_CLK,
17*9702ec00SEddy Petrișor 	MXC_USDHC_CLK,
18*9702ec00SEddy Petrișor 	MXC_FEC_CLK,
19*9702ec00SEddy Petrișor 	MXC_I2C_CLK,
20*9702ec00SEddy Petrișor };
21*9702ec00SEddy Petrișor enum pll_type {
22*9702ec00SEddy Petrișor 	ARM_PLL = 0,
23*9702ec00SEddy Petrișor 	PERIPH_PLL,
24*9702ec00SEddy Petrișor 	ENET_PLL,
25*9702ec00SEddy Petrișor 	DDR_PLL,
26*9702ec00SEddy Petrișor 	VIDEO_PLL,
27*9702ec00SEddy Petrișor };
28*9702ec00SEddy Petrișor 
29*9702ec00SEddy Petrișor unsigned int mxc_get_clock(enum mxc_clock clk);
30*9702ec00SEddy Petrișor void clock_init(void);
31*9702ec00SEddy Petrișor 
32*9702ec00SEddy Petrișor #define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
33*9702ec00SEddy Petrișor 
34*9702ec00SEddy Petrișor #endif /* __ASM_ARCH_CLOCK_H */
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