1 /* 2 * Copyright (C) 2018 Rockchip Electronics Co., Ltd 3 * Author: Zhihuan He <huan.he@rock-chips.com> 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARCH_SDRAM_RV1108_PCTL_PHY_H 8 #define _ASM_ARCH_SDRAM_RV1108_PCTL_PHY_H 9 10 #include <common.h> 11 12 struct ddr_pctl { 13 u32 scfg; 14 u32 sctl; 15 u32 stat; 16 u32 intrstat; 17 u32 reserved0[(0x40-0x10)/4]; 18 u32 mcmd; 19 u32 powctl; 20 u32 powstat; 21 u32 cmdtstat; 22 u32 cmdtstaten; 23 u32 reserved1[(0x60-0x54)/4]; 24 u32 mrrcfg0; 25 u32 mrrstat0; 26 u32 mrrstat1; 27 u32 reserved2[(0x7c-0x6c)/4]; 28 u32 mcfg1; 29 u32 mcfg; 30 u32 ppcfg; 31 u32 mstat; 32 u32 lpddr2zqcfg; 33 u32 reserved3; 34 u32 dtupdes; 35 u32 dtuna; 36 u32 dtune; 37 u32 dtuprd0; 38 u32 dtuprd1; 39 u32 dtuprd2; 40 u32 dtuprd3; 41 u32 dtuawdt; 42 u32 reserved4[(0xc0-0xb4)/4]; 43 u32 togcnt1u; 44 u32 tinit; 45 u32 trsth; 46 u32 togcnt100n; 47 u32 trefi; 48 u32 tmrd; 49 u32 trfc; 50 u32 trp; 51 u32 trtw; 52 u32 tal; 53 u32 tcl; 54 u32 tcwl; 55 u32 tras; 56 u32 trc; 57 u32 trcd; 58 u32 trrd; 59 u32 trtp; 60 u32 twr; 61 u32 twtr; 62 u32 texsr; 63 u32 txp; 64 u32 txpdll; 65 u32 tzqcs; 66 u32 tzqcsi; 67 u32 tdqs; 68 u32 tcksre; 69 u32 tcksrx; 70 u32 tcke; 71 u32 tmod; 72 u32 trstl; 73 u32 tzqcl; 74 u32 tmrr; 75 u32 tckesr; 76 u32 tdpd; 77 u32 trefi_mem_ddr3; 78 u32 reserved5[(0x180-0x14c)/4]; 79 u32 ecccfg; 80 u32 ecctst; 81 u32 eccclr; 82 u32 ecclog; 83 u32 reserved6[(0x200-0x190)/4]; 84 u32 dtuwactl; 85 u32 dturactl; 86 u32 dtucfg; 87 u32 dtuectl; 88 u32 dtuwd0; 89 u32 dtuwd1; 90 u32 dtuwd2; 91 u32 dtuwd3; 92 u32 dtuwdm; 93 u32 dturd0; 94 u32 dturd1; 95 u32 dturd2; 96 u32 dturd3; 97 u32 dtulfsrwd; 98 u32 dtulfsrrd; 99 u32 dtueaf; 100 u32 dfitctrldelay; 101 u32 dfiodtcfg; 102 u32 dfiodtcfg1; 103 u32 dfiodtrankmap; 104 u32 dfitphywrdata; 105 u32 dfitphywrlat; 106 u32 dfitphywrdatalat; 107 u32 reserved7; 108 u32 dfitrddataen; 109 u32 dfitphyrdlat; 110 u32 reserved8[(0x270-0x268)/4]; 111 u32 dfitphyupdtype0; 112 u32 dfitphyupdtype1; 113 u32 dfitphyupdtype2; 114 u32 dfitphyupdtype3; 115 u32 dfitctrlupdmin; 116 u32 dfitctrlupdmax; 117 u32 dfitctrlupddly; 118 u32 reserved9; 119 u32 dfiupdcfg; 120 u32 dfitrefmski; 121 u32 dfitctrlupdi; 122 u32 reserved10[(0x2ac-0x29c)/4]; 123 u32 dfitrcfg0; 124 u32 dfitrstat0; 125 u32 dfitrwrlvlen; 126 u32 dfitrrdlvlen; 127 u32 dfitrrdlvlgateen; 128 u32 dfiststat0; 129 u32 dfistcfg0; 130 u32 dfistcfg1; 131 u32 reserved11; 132 u32 dfitdramclken; 133 u32 dfitdramclkdis; 134 u32 dfistcfg2; 135 u32 dfistparclr; 136 u32 dfistparlog; 137 u32 reserved12[(0x2f0-0x2e4)/4]; 138 u32 dfilpcfg0; 139 u32 reserved13[(0x300-0x2f4)/4]; 140 u32 dfitrwrlvlresp0; 141 u32 dfitrwrlvlresp1; 142 u32 dfitrwrlvlresp2; 143 u32 dfitrrdlvlresp0; 144 u32 dfitrrdlvlresp1; 145 u32 dfitrrdlvlresp2; 146 u32 dfitrwrlvldelay0; 147 u32 dfitrwrlvldelay1; 148 u32 dfitrwrlvldelay2; 149 u32 dfitrrdlvldelay0; 150 u32 dfitrrdlvldelay1; 151 u32 dfitrrdlvldelay2; 152 u32 dfitrrdlvlgatedelay0; 153 u32 dfitrrdlvlgatedelay1; 154 u32 dfitrrdlvlgatedelay2; 155 u32 dfitrcmd; 156 u32 reserved14[(0x3f8-0x340)/4]; 157 u32 ipvr; 158 u32 iptr; 159 }; 160 check_member(ddr_pctl, iptr, 0x03fc); 161 162 struct ddr_phy { 163 u32 phy_reg0; 164 u32 phy_reg1; 165 u32 phy_reg2; 166 u32 phy_reg3; 167 u32 reserved0; 168 u32 phy_reg5; 169 u32 phy_reg6; 170 u32 reserveds1[(0x24-0x1c)/4]; 171 u32 phy_reg9; 172 u32 reserveds2[(0x2c-0x28)/4]; 173 u32 phy_regb; 174 u32 phy_regc; 175 u32 reserveds3[(0x44-0x34)/4]; 176 u32 phy_reg11; 177 u32 phy_reg12; 178 u32 phy_reg13; 179 u32 phy_reg14; 180 u32 reserved4; 181 u32 phy_reg16; 182 u32 phy_reg17; 183 u32 phy_reg18; 184 u32 reserveds5[(0x80-0x64)/4]; 185 u32 phy_reg20; 186 u32 phy_reg21; 187 u32 reserveds6[(0x98-0x88)/4]; 188 u32 phy_reg26; 189 u32 phy_reg27; 190 u32 phy_reg28; 191 u32 reserveds7[(0xac-0xa4)/4]; 192 u32 phy_reg2b; 193 u32 reserveds8[(0xb8-0xb0)/4]; 194 u32 phy_reg2e; 195 u32 phy_reg2f; 196 u32 phy_reg30; 197 u32 phy_reg31; 198 u32 reserveds9[(0xd8-0xc8)/4]; 199 u32 phy_reg36; 200 u32 phy_reg37; 201 u32 phy_reg38; 202 u32 reserveds10[(0xec-0xe4)/4]; 203 u32 phy_reg3b; 204 u32 reserveds11[(0xf8-0xf0)/4]; 205 u32 phy_reg3e; 206 u32 phy_reg3f; 207 u32 reserveds12[(0x1c0-0x100)/4]; 208 u32 phy_reg_skew_cs0data[(0x218-0x1c0)/4]; 209 u32 reserveds13[(0x28c-0x218)/4]; 210 u32 phy_vref; 211 u32 phy_regdll;/*dll bypass switch reg,0x290*/ 212 u32 reserveds14[(0x2c0-0x294)/4]; 213 u32 phy_reg_ca_skew[(0x2f8-0x2c0)/4]; 214 u32 reserveds15[(0x300-0x2f8)/4]; 215 u32 phy_reg_skew_cs1data[(0x358-0x300)/4]; 216 u32 reserveds16[(0x3c0-0x358)/4]; 217 u32 phy_regf0; 218 u32 phy_regf1; 219 u32 reserveds17[(0x3e8-0x3c8)/4]; 220 u32 phy_regfa; 221 u32 phy_regfb; 222 u32 phy_regfc; 223 u32 reserved18; 224 u32 reserved19; 225 u32 phy_regff; 226 }; 227 check_member(ddr_phy, phy_regff, 0x03fc); 228 229 struct ddr_timing { 230 u32 freq; 231 struct pctl_timing { 232 u32 togcnt1u; 233 u32 tinit; 234 u32 trsth; 235 u32 togcnt100n; 236 u32 trefi; 237 u32 tmrd; 238 u32 trfc; 239 u32 trp; 240 u32 trtw; 241 u32 tal; 242 u32 tcl; 243 u32 tcwl; 244 u32 tras; 245 u32 trc; 246 u32 trcd; 247 u32 trrd; 248 u32 trtp; 249 u32 twr; 250 u32 twtr; 251 u32 texsr; 252 u32 txp; 253 u32 txpdll; 254 u32 tzqcs; 255 u32 tzqcsi; 256 u32 tdqs; 257 u32 tcksre; 258 u32 tcksrx; 259 u32 tcke; 260 u32 tmod; 261 u32 trstl; 262 u32 tzqcl; 263 u32 tmrr; 264 u32 tckesr; 265 u32 tdpd; 266 u32 trefi_mem_ddr3; 267 } pctl_timing; 268 struct phy_timing { 269 u32 mr[4]; 270 u32 bl; 271 u32 cl_al; 272 } phy_timing; 273 u32 noc_timing; 274 u32 readlatency; 275 u32 activate; 276 u32 devtodev; 277 }; 278 279 struct ddr_config { 280 /* 281 * 000: lpddr 282 * 001: ddr 283 * 010: ddr2 284 * 011: ddr3 285 * 100: lpddr2-s2 286 * 101: lpddr2-s4 287 * 110: lpddr3 288 */ 289 u32 ddr_type; 290 u32 chn_cnt; 291 u32 rank; 292 u32 cs0_row; 293 u32 cs1_row; 294 295 /* 2: 4bank, 3: 8bank */ 296 u32 bank; 297 u32 col; 298 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ 299 u32 dbw; 300 /* bw(0: 8bit, 1: 16bit, 2: 32bit) */ 301 u32 bw; 302 }; 303 304 enum { 305 PHY_LOW_SPEED_MHZ = 400, 306 /* PHY_REG0 */ 307 CHN_ENABLE_SHIFT = 4, 308 DQ_16BIT_EN_MASK = 3 << 4, 309 DQ_16BIT_EN = 3 << 4, 310 DQ_32BIT_EN_MASK = 0xf << 4, 311 DQ_32BIT_EN = 0xf << 4, 312 RESET_DIGITAL_CORE_SHIFT = 3, 313 RESET_DIGITAL_CORE_MASK = 1 << RESET_DIGITAL_CORE_SHIFT, 314 RESET_DIGITAL_CORE_ACT = 0, 315 RESET_DIGITAL_CORE_DIS = 1, 316 RESET_ANALOG_LOGIC_SHIFT = 2, 317 RESET_ANALOG_LOGIC_MASK = 1 << RESET_ANALOG_LOGIC_SHIFT, 318 RESET_ANALOG_LOGIC_ACT = 0, 319 RESET_ANALOG_LOGIC_DIS = 1, 320 321 /* PHY_REG1 */ 322 MEMORY_SELECT_DDR3 = 0, 323 PHY_BL_8 = 1 << 2, 324 325 /* PHY_REG2 */ 326 DQS_GATE_TRAINING_SEL_CS0 = 1 << 5, 327 DQS_GATE_TRAINING_ACT = 1, 328 DQS_GATE_TRAINING_DIS = 0, 329 330 /* PHY_REG12 */ 331 CMD_PRCOMP_SHIFT = 3, 332 CMD_PRCOMP_MASK = 0x1f << CMD_PRCOMP_SHIFT, 333 334 /* DDRPHY_REG13 */ 335 CMD_DLL_BYPASS_SHIFT = 4, 336 CMD_DLL_BYPASS = 1, 337 CMD_DLL_BYPASS_MASK = 1, 338 CMD_DLL_BYPASS_DISABLE = 0, 339 340 /* DDRPHY_REG14 */ 341 CK_DLL_BYPASS_SHIFT = 3, 342 CK_DLL_BYPASS = 1, 343 CK_DLL_BYPASS_DISABLE = 0, 344 345 /* DDRPHY_REG26 */ 346 LEFT_CHN_A_DQ_DLL_SHIFT = 4, 347 LEFT_CHN_A_DQ_DLL_BYPASS = 1, 348 LEFT_CHN_A_DQ_DLL_BYPASS_MASK = 1, 349 LEFT_CHN_A_DQ_DLL_BYPASS_DIS = 0, 350 351 /* DDRPHY_REG27 */ 352 LEFT_CHN_A_DQS_DLL_SHIFT = 3, 353 LEFT_CHN_A_DQS_DLL_BYPASS = 1, 354 LEFT_CHN_A_DQS_DLL_BYPASS_DIS = 0, 355 356 /* DDRPHY_REG28 */ 357 LEFT_CHN_A_READ_DQS_45_DELAY = 2, 358 359 /* DDRPHY_REG36 */ 360 RIGHT_CHN_A_DQ_DLL_SHIFT = 4, 361 RIGHT_CHN_A_DQ_DLL_BYPASS = 1, 362 RIGHT_CHN_A_DQ_DLL_BYPASS_MASK = 1, 363 RIGHT_CHN_A_DQ_DLL_BYPASS_DIS = 0, 364 365 /* DDRPHY_REG37 */ 366 RIGHT_CHN_A_DQS_DLL_SHIFT = 3, 367 RIGHT_CHN_A_DQS_DLL_BYPASS = 1, 368 RIGHT_CHN_A_DQS_DLL_BYPASS_DIS = 0, 369 370 /* DDRPHY_REG38 */ 371 RIGHT_CHN_A_READ_DQS_45_DELAY = 2, 372 373 /* PHY_REGDLL */ 374 RIGHT_CHN_A_TX_DQ_BYPASS_SHIFT = 2, 375 RIGHT_CHN_A_TX_DQ_BYPASS_SET = 1, 376 RIGHT_CHN_A_TX_DQ_BYPASS_DIS = 0, 377 LEFT_CHN_A_TX_DQ_BYPASS_SHIFT = 1, 378 LEFT_CHN_A_TX_DQ_BYPASS_SET = 1, 379 LEFT_CHN_A_TX_DQ_BYPASS_DIS = 0, 380 CMD_CK_DLL_BYPASS_SHIFT = 0, 381 CMD_CK_DLL_BYPASS_SET = 1, 382 CMD_CK_DLL_BYPASS_DIS = 0, 383 384 /* PHY_REGFF */ 385 CHN_A_TRAINING_DONE_MASK = 3, 386 CHN_A_HIGH_8BIT_TRAINING_DONE = 1 << 1, 387 CHN_A_LOW_8BIT_TRAINING_DONE = 1, 388 }; 389 390 /*PCTL*/ 391 enum { 392 /* PCTL_SCTL */ 393 INIT_STATE = 0, 394 CFG_STATE = 1, 395 GO_STATE = 2, 396 SLEEP_STATE = 3, 397 WAKEUP_STATE = 4, 398 399 /* PCTL_STAT*/ 400 PCTL_CTL_STAT_MASK = 0x7, 401 INIT_MEM = 0, 402 CONFIG = 1, 403 CONFIG_REQ = 2, 404 ACCESS = 3, 405 ACCESS_REQ = 4, 406 LOW_POWER = 5, 407 LOW_POWER_ENTRY_REQ = 6, 408 LOW_POWER_EXIT_REQ = 7, 409 410 /* PCTL_MCMD */ 411 START_CMD = 0x80000000, 412 RANK_SEL_SHIFT = 20, 413 RANK_SEL_CS0 = 1, 414 RANK_SEL_CS1 = 2, 415 RANK_SEL_CS0_CS1 = 3, 416 BANK_ADDR_SHIFT = 17, 417 BANK_ADDR_MASK = 0x7, 418 CMD_ADDR_SHIFT = 4, 419 CMD_ADDR_MASK = 0x1fff, 420 DDR3_DLL_RESET = 1 << 8, 421 DESELECT_CMD = 0x0, 422 PREA_CMD = 0x1, 423 REF_CMD = 0x2, 424 MRS_CMD = 0x3, 425 ZQCS_CMD = 0x4, 426 ZQCL_CMD = 0x5, 427 RSTL_CMD = 0x6, 428 MPR_CMD = 0x8, 429 DFICTRLUPD_CMD = 0xa, 430 MR0 = 0x0, 431 MR1 = 0x1, 432 MR2 = 0x2, 433 MR3 = 0x3, 434 435 /* PCTL_POWCTL */ 436 POWER_UP_START = 1, 437 POWER_UP_START_MASK = 1, 438 439 /* PCTL_POWSTAT */ 440 POWER_UP_DONE = 1, 441 442 /*PCTL_PPCFG*/ 443 PPMEM_EN_MASK = 1, 444 PPMEM_EN = 1, 445 PPMEM_DIS = 0, 446 /* PCTL_TREFI */ 447 UPD_REF = 0x80000000, 448 449 /* PCTL_DFISTCFG0 */ 450 DFI_DATA_BYTE_DISABLE_EN_SHIFT = 2, 451 DFI_DATA_BYTE_DISABLE_EN = 1, 452 DFI_FREQ_RATIO_EN_SHIFT = 1, 453 DFI_FREQ_RATIO_EN = 1, 454 DFI_INIT_START_SHIFT = 0, 455 DFI_INIT_START_EN = 1, 456 457 /* PCTL_DFISTCFG1 */ 458 DFI_DRAM_CLK_DISABLE_EN_DPD_SHIFT = 1, 459 DFI_DRAM_CLK_DISABLE_EN_DPD = 1, 460 DFI_DRAM_CLK_DISABLE_EN_SHIFT = 0, 461 DFI_DRAM_CLK_DISABLE_EN = 1, 462 463 /* PCTL_DFISTCFG2 */ 464 PARITY_EN_SHIFT = 1, 465 PARITY_EN = 1, 466 PARITY_INTR_EN_SHIFT = 0, 467 PARITY_INTR_EN = 1, 468 469 /* PCTL_DFILPCFG0 */ 470 DFI_LP_EN_SR_SHIFT = 8, 471 DFI_LP_EN_SR = 1, 472 DFI_LP_WAKEUP_SR_SHIFT = 12, 473 DFI_LP_WAKEUP_SR_32_CYCLES = 1, 474 DFI_TLP_RESP_SHIFT = 16, 475 DFI_TLP_RESP = 5, 476 477 /* PCTL_DFITPHYUPDTYPE0 */ 478 TPHYUPD_TYPE0 = 1, 479 480 /* PCTL_DFITPHYRDLAT */ 481 TPHY_RDLAT = 0xd, 482 483 /* PCTL_DFITPHYWRDATA */ 484 TPHY_WRDATA = 0x0, 485 486 /* PCTL_DFIUPDCFG */ 487 DFI_PHYUPD_DISABLE = 0 << 1, 488 DFI_CTRLUPD_DISABLE = 0, 489 490 /* PCTL_DFIODTCFG */ 491 RANK0_ODT_WRITE_SEL_SHIFT = 3, 492 RANK0_ODT_WRITE_SEL = 1, 493 RANK1_ODT_WRITE_SEL_SHIFT = 11, 494 RANK1_ODT_WRITE_SEL = 1, 495 496 /* PCTL_DFIODTCFG1 */ 497 ODT_LEN_BL8_W_SHIFT = 16, 498 ODT_LEN_BL8_W = 7, 499 500 /* PCTL_MCFG */ 501 MDDR_LPDDR23_CLOCK_STOP_IDLE_DIS = 0 << 24, 502 DDR3_EN = 1 << 5, 503 MEM_BL_8 = 1, 504 TFAW_CFG_5_TDDR = 1 << 18, 505 PD_EXIT_SLOW_EXIT_MODE = 0 << 17, 506 PD_TYPE_ACT_PD = 1 << 16, 507 PD_IDLE_DISABLE = 0 << 8, 508 PD_IDLE_MASK = 0xff << 8, 509 PD_IDLE_SHIFT = 8, 510 511 /* PCTL_MCFG1 */ 512 SR_IDLE_MASK = 0xff, 513 HW_EXIT_IDLE_EN_SHIFT = 31, 514 HW_EXIT_IDLE_EN_MASK = 1 << HW_EXIT_IDLE_EN_SHIFT, 515 HW_EXIT_IDLE_EN = 1 << HW_EXIT_IDLE_EN_SHIFT, 516 517 /* PCTL_SCFG */ 518 HW_LOW_POWER_EN = 1, 519 }; 520 521 enum { 522 /* PHY_DDR3_RON_RTT */ 523 PHY_RON_RTT_DISABLE = 0, 524 PHY_RON_RTT_451OHM = 1, 525 PHY_RON_RTT_225OHM = 2, 526 PHY_RON_RTT_150OHM = 3, 527 PHY_RON_RTT_112OHM = 4, 528 PHY_RON_RTT_90OHM = 5, 529 PHY_RON_RTT_75OHM = 6, 530 PHY_RON_RTT_64OHM = 7, 531 532 PHY_RON_RTT_56OHM = 16, 533 PHY_RON_RTT_50OHM = 17, 534 PHY_RON_RTT_45OHM = 18, 535 PHY_RON_RTT_41OHM = 19, 536 PHY_RON_RTT_37OHM = 20, 537 PHY_RON_RTT_34OHM = 21, 538 PHY_RON_RTT_33OHM = 22, 539 PHY_RON_RTT_30OHM = 23, 540 541 PHY_RON_RTT_28OHM = 24, 542 PHY_RON_RTT_26OHM = 25, 543 PHY_RON_RTT_25OHM = 26, 544 PHY_RON_RTT_23OHM = 27, 545 PHY_RON_RTT_22OHM = 28, 546 PHY_RON_RTT_21OHM = 29, 547 PHY_RON_RTT_20OHM = 30, 548 PHY_RON_RTT_19OHM = 31, 549 }; 550 551 #endif 552