1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef _ASM_ARCH_SDRAM_RK3568_H 7 #define _ASM_ARCH_SDRAM_RK3568_H 8 9 #include <asm/arch-rockchip/sdram.h> 10 #include <asm/arch-rockchip/sdram_common.h> 11 12 /* store result of read and write training, for ddr_dq_eye tool in u-boot */ 13 #define RW_TRN_RESULT_ADDR (0x2000000 + 0x8000) /* 32M + 32k */ 14 15 #undef FSP_NUM 16 #undef CS_NUM 17 #undef BYTE_NUM 18 19 #define FSP_NUM 4 20 #define CS_NUM 4 21 #define BYTE_NUM 5 22 #define RD_DESKEW_NUM 128 23 #define WR_DESKEW_NUM 256 24 25 #define LP4_WIDTH_REF_MHZ_H 1560 26 #define LP4_RD_WIDTH_REF_H 25 27 #define LP4_WR_WIDTH_REF_H 24 28 29 #define LP4_WIDTH_REF_MHZ_L 1184 30 #define LP4_RD_WIDTH_REF_L 30 31 #define LP4_WR_WIDTH_REF_L 29 32 33 #define DDR4_WIDTH_REF_MHZ_H 1560 34 #define DDR4_RD_WIDTH_REF_H 30 35 #define DDR4_WR_WIDTH_REF_H 22 36 37 #define DDR4_WIDTH_REF_MHZ_L 1184 38 #define DDR4_RD_WIDTH_REF_L 32 39 #define DDR4_WR_WIDTH_REF_L 26 40 41 #define LP3_WIDTH_REF_MHZ_H 1184 42 #define LP3_RD_WIDTH_REF_H 34 43 #define LP3_WR_WIDTH_REF_H 25 44 45 #define LP3_WIDTH_REF_MHZ_L 920 46 #define LP3_RD_WIDTH_REF_L 39 47 #define LP3_WR_WIDTH_REF_L 28 48 49 #define DDR3_WIDTH_REF_MHZ_H 1184 50 #define DDR3_RD_WIDTH_REF_H 32 51 #define DDR3_WR_WIDTH_REF_H 31 52 53 #define DDR3_WIDTH_REF_MHZ_L 920 54 #define DDR3_RD_WIDTH_REF_L 39 55 #define DDR3_WR_WIDTH_REF_L 34 56 57 #endif /* _ASM_ARCH_SDRAM_RK3568_H */ 58