1 /* 2 * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARCH_SDRAM_RK3399_H 8 #define _ASM_ARCH_SDRAM_RK3399_H 9 #include <asm/arch/sdram_share.h> 10 11 struct rk3399_ddr_pctl_regs { 12 u32 denali_ctl[332]; 13 }; 14 15 struct rk3399_ddr_publ_regs { 16 u32 denali_phy[959]; 17 }; 18 19 struct rk3399_ddr_pi_regs { 20 u32 denali_pi[200]; 21 }; 22 23 struct rk3399_ddr_cic_regs { 24 u32 cic_ctrl0; 25 u32 cic_ctrl1; 26 u32 cic_idle_th; 27 u32 cic_cg_wait_th; 28 u32 cic_status0; 29 u32 cic_status1; 30 u32 cic_ctrl2; 31 u32 cic_ctrl3; 32 u32 cic_ctrl4; 33 }; 34 35 /* DENALI_CTL_00 */ 36 #define START 1 37 38 /* DENALI_CTL_68 */ 39 #define PWRUP_SREFRESH_EXIT (1 << 16) 40 41 /* DENALI_CTL_274 */ 42 #define MEM_RST_VALID 1 43 44 struct rk3399_sdram_channel { 45 struct sdram_cap_info cap_info; 46 struct sdram_msch_timings noc_timings; 47 }; 48 49 struct rk3399_sdram_params { 50 struct rk3399_sdram_channel ch[2]; 51 struct sdram_base_params base; 52 struct rk3399_ddr_pctl_regs pctl_regs; 53 struct rk3399_ddr_pi_regs pi_regs; 54 struct rk3399_ddr_publ_regs phy_regs; 55 }; 56 57 #define PI_CA_TRAINING (1 << 0) 58 #define PI_WRITE_LEVELING (1 << 1) 59 #define PI_READ_GATE_TRAINING (1 << 2) 60 #define PI_READ_LEVELING (1 << 3) 61 #define PI_WDQ_LEVELING (1 << 4) 62 #define PI_FULL_TRAINING 0xff 63 64 enum { 65 STRIDE_128B = 0, 66 STRIDE_256B = 1, 67 STRIDE_512B = 2, 68 STRIDE_4KB = 3, 69 UN_STRIDE = 4, 70 PART_STRIDE = 5 71 }; 72 73 #endif 74