1 /* 2 * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARCH_SDRAM_RK3399_H 8 #define _ASM_ARCH_SDRAM_RK3399_H 9 10 struct rk3399_ddr_pctl_regs { 11 u32 denali_ctl[332]; 12 }; 13 14 struct rk3399_ddr_publ_regs { 15 u32 denali_phy[959]; 16 }; 17 18 struct rk3399_ddr_pi_regs { 19 u32 denali_pi[200]; 20 }; 21 22 struct rk3399_msch_regs { 23 u32 coreid; 24 u32 revisionid; 25 u32 ddrconf; 26 u32 ddrsize; 27 u32 ddrtiminga0; 28 u32 ddrtimingb0; 29 u32 ddrtimingc0; 30 u32 devtodev0; 31 u32 reserved0[(0x110 - 0x20) / 4]; 32 u32 ddrmode; 33 u32 reserved1[(0x1000 - 0x114) / 4]; 34 u32 agingx0; 35 }; 36 37 struct rk3399_msch_timings { 38 u32 ddrtiminga0; 39 u32 ddrtimingb0; 40 u32 ddrtimingc0; 41 u32 devtodev0; 42 u32 ddrmode; 43 u32 agingx0; 44 }; 45 46 struct rk3399_ddr_cic_regs { 47 u32 cic_ctrl0; 48 u32 cic_ctrl1; 49 u32 cic_idle_th; 50 u32 cic_cg_wait_th; 51 u32 cic_status0; 52 u32 cic_status1; 53 u32 cic_ctrl2; 54 u32 cic_ctrl3; 55 u32 cic_ctrl4; 56 }; 57 58 /* DENALI_CTL_00 */ 59 #define START 1 60 61 /* DENALI_CTL_68 */ 62 #define PWRUP_SREFRESH_EXIT (1 << 16) 63 64 /* DENALI_CTL_274 */ 65 #define MEM_RST_VALID 1 66 67 struct rk3399_sdram_channel { 68 unsigned int rank; 69 /* dram column number, 0 means this channel is invalid */ 70 unsigned int col; 71 /* dram bank number, 3:8bank, 2:4bank */ 72 unsigned int bk; 73 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ 74 unsigned int bw; 75 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ 76 unsigned int dbw; 77 /* 78 * row_3_4 = 1: 6Gb or 12Gb die 79 * row_3_4 = 0: normal die, power of 2 80 */ 81 unsigned int row_3_4; 82 unsigned int cs0_row; 83 unsigned int cs1_row; 84 unsigned int ddrconfig; 85 struct rk3399_msch_timings noc_timings; 86 }; 87 88 struct rk3399_base_params { 89 unsigned int ddr_freq; 90 unsigned int dramtype; 91 unsigned int num_channels; 92 unsigned int stride; 93 unsigned int odt; 94 }; 95 96 struct rk3399_sdram_params { 97 struct rk3399_sdram_channel ch[2]; 98 struct rk3399_base_params base; 99 struct rk3399_ddr_pctl_regs pctl_regs; 100 struct rk3399_ddr_pi_regs pi_regs; 101 struct rk3399_ddr_publ_regs phy_regs; 102 }; 103 104 #define PI_CA_TRAINING (1 << 0) 105 #define PI_WRITE_LEVELING (1 << 1) 106 #define PI_READ_GATE_TRAINING (1 << 2) 107 #define PI_READ_LEVELING (1 << 3) 108 #define PI_WDQ_LEVELING (1 << 4) 109 #define PI_FULL_TRAINING 0xff 110 111 #endif 112