1 /* 2 * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARCH_SDRAM_RK3328_H 8 #define _ASM_ARCH_SDRAM_RK3328_H 9 10 #define SR_IDLE 93 11 #define PD_IDLE 13 12 #define SDRAM_ADDR 0x00000000 13 #define PATTERN (0x5aa5f00f) 14 15 /* ddr pctl registers define */ 16 #define DDR_PCTL2_MSTR 0x0 17 #define DDR_PCTL2_STAT 0x4 18 #define DDR_PCTL2_MSTR1 0x8 19 #define DDR_PCTL2_MRCTRL0 0x10 20 #define DDR_PCTL2_MRCTRL1 0x14 21 #define DDR_PCTL2_MRSTAT 0x18 22 #define DDR_PCTL2_MRCTRL2 0x1c 23 #define DDR_PCTL2_DERATEEN 0x20 24 #define DDR_PCTL2_DERATEINT 0x24 25 #define DDR_PCTL2_PWRCTL 0x30 26 #define DDR_PCTL2_PWRTMG 0x34 27 #define DDR_PCTL2_HWLPCTL 0x38 28 #define DDR_PCTL2_RFSHCTL0 0x50 29 #define DDR_PCTL2_RFSHCTL1 0x54 30 #define DDR_PCTL2_RFSHCTL2 0x58 31 #define DDR_PCTL2_RFSHCTL4 0x5c 32 #define DDR_PCTL2_RFSHCTL3 0x60 33 #define DDR_PCTL2_RFSHTMG 0x64 34 #define DDR_PCTL2_RFSHTMG1 0x68 35 #define DDR_PCTL2_RFSHCTL5 0x6c 36 #define DDR_PCTL2_INIT0 0xd0 37 #define DDR_PCTL2_INIT1 0xd4 38 #define DDR_PCTL2_INIT2 0xd8 39 #define DDR_PCTL2_INIT3 0xdc 40 #define DDR_PCTL2_INIT4 0xe0 41 #define DDR_PCTL2_INIT5 0xe4 42 #define DDR_PCTL2_INIT6 0xe8 43 #define DDR_PCTL2_INIT7 0xec 44 #define DDR_PCTL2_DIMMCTL 0xf0 45 #define DDR_PCTL2_RANKCTL 0xf4 46 #define DDR_PCTL2_CHCTL 0xfc 47 #define DDR_PCTL2_DRAMTMG0 0x100 48 #define DDR_PCTL2_DRAMTMG1 0x104 49 #define DDR_PCTL2_DRAMTMG2 0x108 50 #define DDR_PCTL2_DRAMTMG3 0x10c 51 #define DDR_PCTL2_DRAMTMG4 0x110 52 #define DDR_PCTL2_DRAMTMG5 0x114 53 #define DDR_PCTL2_DRAMTMG6 0x118 54 #define DDR_PCTL2_DRAMTMG7 0x11c 55 #define DDR_PCTL2_DRAMTMG8 0x120 56 #define DDR_PCTL2_DRAMTMG9 0x124 57 #define DDR_PCTL2_DRAMTMG10 0x128 58 #define DDR_PCTL2_DRAMTMG11 0x12c 59 #define DDR_PCTL2_DRAMTMG12 0x130 60 #define DDR_PCTL2_DRAMTMG13 0x134 61 #define DDR_PCTL2_DRAMTMG14 0x138 62 #define DDR_PCTL2_DRAMTMG15 0x13c 63 #define DDR_PCTL2_DRAMTMG16 0x140 64 #define DDR_PCTL2_ZQCTL0 0x180 65 #define DDR_PCTL2_ZQCTL1 0x184 66 #define DDR_PCTL2_ZQCTL2 0x188 67 #define DDR_PCTL2_ZQSTAT 0x18c 68 #define DDR_PCTL2_DFITMG0 0x190 69 #define DDR_PCTL2_DFITMG1 0x194 70 #define DDR_PCTL2_DFILPCFG0 0x198 71 #define DDR_PCTL2_DFILPCFG1 0x19c 72 #define DDR_PCTL2_DFIUPD0 0x1a0 73 #define DDR_PCTL2_DFIUPD1 0x1a4 74 #define DDR_PCTL2_DFIUPD2 0x1a8 75 #define DDR_PCTL2_DFIMISC 0x1b0 76 #define DDR_PCTL2_DFITMG2 0x1b4 77 #define DDR_PCTL2_DFITMG3 0x1b8 78 #define DDR_PCTL2_DFISTAT 0x1bc 79 #define DDR_PCTL2_DBICTL 0x1c0 80 #define DDR_PCTL2_ADDRMAP0 0x200 81 #define DDR_PCTL2_ADDRMAP1 0x204 82 #define DDR_PCTL2_ADDRMAP2 0x208 83 #define DDR_PCTL2_ADDRMAP3 0x20c 84 #define DDR_PCTL2_ADDRMAP4 0x210 85 #define DDR_PCTL2_ADDRMAP5 0x214 86 #define DDR_PCTL2_ADDRMAP6 0x218 87 #define DDR_PCTL2_ADDRMAP7 0x21c 88 #define DDR_PCTL2_ADDRMAP8 0x220 89 #define DDR_PCTL2_ADDRMAP9 0x224 90 #define DDR_PCTL2_ADDRMAP10 0x228 91 #define DDR_PCTL2_ADDRMAP11 0x22c 92 #define DDR_PCTL2_ODTCFG 0x240 93 #define DDR_PCTL2_ODTMAP 0x244 94 #define DDR_PCTL2_SCHED 0x250 95 #define DDR_PCTL2_SCHED1 0x254 96 #define DDR_PCTL2_PERFHPR1 0x25c 97 #define DDR_PCTL2_PERFLPR1 0x264 98 #define DDR_PCTL2_PERFWR1 0x26c 99 #define DDR_PCTL2_DQMAP0 0x280 100 #define DDR_PCTL2_DQMAP1 0x284 101 #define DDR_PCTL2_DQMAP2 0x288 102 #define DDR_PCTL2_DQMAP3 0x28c 103 #define DDR_PCTL2_DQMAP4 0x290 104 #define DDR_PCTL2_DQMAP5 0x294 105 #define DDR_PCTL2_DBG0 0x300 106 #define DDR_PCTL2_DBG1 0x304 107 #define DDR_PCTL2_DBGCAM 0x308 108 #define DDR_PCTL2_DBGCMD 0x30c 109 #define DDR_PCTL2_DBGSTAT 0x310 110 #define DDR_PCTL2_SWCTL 0x320 111 #define DDR_PCTL2_SWSTAT 0x324 112 #define DDR_PCTL2_POISONCFG 0x36c 113 #define DDR_PCTL2_POISONSTAT 0x370 114 #define DDR_PCTL2_ADVECCINDEX 0x374 115 #define DDR_PCTL2_ADVECCSTAT 0x378 116 #define DDR_PCTL2_PSTAT 0x3fc 117 #define DDR_PCTL2_PCCFG 0x400 118 #define DDR_PCTL2_PCFGR_n 0x404 119 #define DDR_PCTL2_PCFGW_n 0x408 120 #define DDR_PCTL2_PCTRL_n 0x490 121 122 /* PCTL2_MRSTAT */ 123 #define MR_WR_BUSY BIT(0) 124 125 /* PHY_REG0 */ 126 #define DIGITAL_DERESET BIT(3) 127 #define ANALOG_DERESET BIT(2) 128 #define DIGITAL_RESET (0 << 3) 129 #define ANALOG_RESET (0 << 2) 130 131 /* PHY_REG1 */ 132 #define PHY_DDR2 (0) 133 #define PHY_LPDDR2 (1) 134 #define PHY_DDR3 (2) 135 #define PHY_LPDDR3 (3) 136 #define PHY_DDR4 (4) 137 #define PHY_BL_4 (0 << 2) 138 #define PHY_BL_8 BIT(2) 139 140 /* PHY_REG2 */ 141 #define PHY_DTT_EN BIT(0) 142 #define PHY_DTT_DISB (0 << 0) 143 #define PHY_WRITE_LEVELING_EN BIT(2) 144 #define PHY_WRITE_LEVELING_DISB (0 << 2) 145 #define PHY_SELECT_CS0 (2) 146 #define PHY_SELECT_CS1 (1) 147 #define PHY_SELECT_CS0_1 (0) 148 #define PHY_WRITE_LEVELING_SELECTCS(n) (n << 6) 149 #define PHY_DATA_TRAINING_SELECTCS(n) (n << 4) 150 151 #define PHY_DDR3_RON_RTT_DISABLE (0) 152 #define PHY_DDR3_RON_RTT_451ohm (1) 153 #define PHY_DDR3_RON_RTT_225ohm (2) 154 #define PHY_DDR3_RON_RTT_150ohm (3) 155 #define PHY_DDR3_RON_RTT_112ohm (4) 156 #define PHY_DDR3_RON_RTT_90ohm (5) 157 #define PHY_DDR3_RON_RTT_75ohm (6) 158 #define PHY_DDR3_RON_RTT_64ohm (7) 159 #define PHY_DDR3_RON_RTT_56ohm (16) 160 #define PHY_DDR3_RON_RTT_50ohm (17) 161 #define PHY_DDR3_RON_RTT_45ohm (18) 162 #define PHY_DDR3_RON_RTT_41ohm (19) 163 #define PHY_DDR3_RON_RTT_37ohm (20) 164 #define PHY_DDR3_RON_RTT_34ohm (21) 165 #define PHY_DDR3_RON_RTT_33ohm (22) 166 #define PHY_DDR3_RON_RTT_30ohm (23) 167 #define PHY_DDR3_RON_RTT_28ohm (24) 168 #define PHY_DDR3_RON_RTT_26ohm (25) 169 #define PHY_DDR3_RON_RTT_25ohm (26) 170 #define PHY_DDR3_RON_RTT_23ohm (27) 171 #define PHY_DDR3_RON_RTT_22ohm (28) 172 #define PHY_DDR3_RON_RTT_21ohm (29) 173 #define PHY_DDR3_RON_RTT_20ohm (30) 174 #define PHY_DDR3_RON_RTT_19ohm (31) 175 176 #define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0) 177 #define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1) 178 #define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2) 179 #define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3) 180 #define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4) 181 #define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5) 182 #define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6) 183 #define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7) 184 #define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16) 185 #define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17) 186 #define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18) 187 #define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19) 188 #define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20) 189 #define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21) 190 #define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22) 191 #define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23) 192 #define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24) 193 #define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25) 194 #define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26) 195 #define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27) 196 #define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28) 197 #define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29) 198 #define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30) 199 #define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31) 200 201 /* noc registers define */ 202 #define DDRCONF 0x8 203 #define DDRTIMING 0xc 204 #define DDRMODE 0x10 205 #define READLATENCY 0x14 206 #define AGING0 0x18 207 #define AGING1 0x1c 208 #define AGING2 0x20 209 #define AGING3 0x24 210 #define AGING4 0x28 211 #define AGING5 0x2c 212 #define ACTIVATE 0x38 213 #define DEVTODEV 0x3c 214 #define DDR4TIMING 0x40 215 216 /* DDR GRF */ 217 #define DDR_GRF_CON(n) (0 + (n) * 4) 218 #define DDR_GRF_STATUS_BASE (0X100) 219 #define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) 220 221 /* 222 * sys_reg bitfield struct 223 * [31] row_3_4_ch1 224 * [30] row_3_4_ch0 225 * [29:28] chinfo 226 * [27] rank_ch1 227 * [26:25] col_ch1 228 * [24] bk_ch1 229 * [23:22] cs0_row_ch1 230 * [21:20] cs1_row_ch1 231 * [19:18] bw_ch1 232 * [17:16] dbw_ch1; 233 * [15:13] ddrtype 234 * [12] channelnum 235 * [11] rank_ch0 236 * [10:9] col_ch0 237 * [8] bk_ch0 238 * [7:6] cs0_row_ch0 239 * [5:4] cs1_row_ch0 240 * [3:2] bw_ch0 241 * [1:0] dbw_ch0 242 */ 243 #define SYS_REG_ENC_ROW_3_4(n) ((n) << 30) 244 #define SYS_REG_DEC_ROW_3_4(n) ((n >> 30) & 0x1) 245 #define SYS_REG_ENC_CHINFO() (1 << 28) 246 #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) 247 #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) 248 #define SYS_REG_DEC_NUM_CH(n) (1 + ((n >> 12) & 0x1)) 249 #define SYS_REG_ENC_RANK(n) (((n) - 1) << 11) 250 #define SYS_REG_DEC_RANK(n) (1 + ((n >> 11) & 0x1)) 251 #define SYS_REG_ENC_COL(n) (((n) - 9) << 9) 252 #define SYS_REG_DEC_COL(n) (9 + ((n >> 9) & 0x3)) 253 #define SYS_REG_ENC_BK(n) (((n) == 3 ? 0 : 1) << 8) 254 #define SYS_REG_DEC_BK(n) (3 - ((n >> 8) & 0x1)) 255 #define SYS_REG_ENC_CS0_ROW(n) (((n) - 13) << 6) 256 #define SYS_REG_DEC_CS0_ROW(n) (13 + ((n >> 6) & 0x3)) 257 #define SYS_REG_ENC_CS1_ROW(n) (((n) - 13) << 4) 258 #define SYS_REG_DEC_CS1_ROW(n) (13 + ((n >> 4) & 0x3)) 259 #define SYS_REG_ENC_BW(n) ((2 >> (n)) << 2) 260 #define SYS_REG_DEC_BW(n) (2 >> ((n >> 2) & 0x3)) 261 #define SYS_REG_ENC_DBW(n) ((2 >> (n)) << 0) 262 #define SYS_REG_DEC_DBW(n) (2 >> ((n >> 0) & 0x3)) 263 264 /* CRU_SOFTRESET_CON5 */ 265 #define ddrphy_psrstn_req(n) (((0x1 << 15) << 16) | (n << 15)) 266 #define ddrphy_srstn_req(n) (((0x1 << 14) << 16) | (n << 14)) 267 #define ddrctrl_psrstn_req(n) (((0x1 << 13) << 16) | (n << 13)) 268 #define ddrctrl_srstn_req(n) (((0x1 << 12) << 16) | (n << 12)) 269 #define ddrmsch_srstn_req(n) (((0x1 << 11) << 16) | (n << 11)) 270 #define msch_srstn_req(n) (((0x1 << 9) << 16) | (n << 9)) 271 #define dfimon_srstn_req(n) (((0x1 << 8) << 16) | (n << 8)) 272 #define grf_ddr_srstn_req(n) (((0x1 << 7) << 16) | (n << 7)) 273 /* CRU_SOFTRESET_CON9 */ 274 #define ddrctrl_asrstn_req(n) (((0x1 << 9) << 16) | (n << 9)) 275 276 /* CRU register */ 277 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) 278 #define CRU_MODE (0x80) 279 #define CRU_GLB_CNT_TH (0x90) 280 #define CRU_CLKSEL_CON_BASE 0x100 281 #define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON_BASE + ((i) * 4)) 282 #define CRU_CLKGATE_CON_BASE 0x200 283 #define CRU_CLKGATE_CON(i) (CRU_CLKGATE_CON_BASE + ((i) * 4)) 284 #define CRU_CLKSFTRST_CON_BASE 0x300 285 #define CRU_CLKSFTRST_CON(i) (CRU_CLKSFTRST_CON_BASE + ((i) * 4)) 286 287 /* CRU_PLL_CON0 */ 288 #define PB(n) ((0x1 << (15 + 16)) | ((n) << 15)) 289 #define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12)) 290 #define FBDIV(n) ((0xFFF << 16) | (n)) 291 292 /* CRU_PLL_CON1 */ 293 #define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15)) 294 #define RST(n) ((0x1 << (14 + 16)) | ((n) << 14)) 295 #define PD(n) ((0x1 << (13 + 16)) | ((n) << 13)) 296 #define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12)) 297 #define LOCK(n) (((n) >> 10) & 0x1) 298 #define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6)) 299 #define REFDIV(n) ((0x3F << 16) | (n)) 300 301 union noc_ddrtiming { 302 u32 d32; 303 struct { 304 unsigned acttoact:6; 305 unsigned rdtomiss:6; 306 unsigned wrtomiss:6; 307 unsigned burstlen:3; 308 unsigned rdtowr:5; 309 unsigned wrtord:5; 310 unsigned bwratio:1; 311 } b; 312 } NOC_TIMING_T; 313 314 union noc_activate { 315 u32 d32; 316 struct { 317 unsigned rrd:4; 318 unsigned faw:6; 319 unsigned fawbank:1; 320 unsigned reserved1:21; 321 } b; 322 }; 323 324 union noc_devtodev { 325 u32 d32; 326 struct { 327 unsigned busrdtord:2; 328 unsigned busrdtowr:2; 329 unsigned buswrtord:2; 330 unsigned reserved2:26; 331 } b; 332 }; 333 334 union noc_ddr4timing { 335 u32 d32; 336 struct { 337 unsigned ccdl:3; 338 unsigned wrtordl:5; 339 unsigned rrdl:4; 340 unsigned reserved2:20; 341 } b; 342 }; 343 344 union noc_ddrmode { 345 u32 d32; 346 struct { 347 unsigned autoprecharge:1; 348 unsigned bwratioextended:1; 349 unsigned reserved3:30; 350 } b; 351 }; 352 353 u16 ddr_cfg_2_rbc[] = { 354 /*************************** 355 * [5:4] row(13+n) 356 * [3] cs(0:0 cs, 1:2 cs) 357 * [2] bank(0:0bank,1:8bank) 358 * [1:0] col(11+n) 359 ****************************/ 360 /* row, cs, bank, col */ 361 ((3 << 4) | (0 << 3) | (1 << 2) | 0), 362 ((3 << 4) | (0 << 3) | (1 << 2) | 1), 363 ((2 << 4) | (0 << 3) | (1 << 2) | 2), 364 ((3 << 4) | (0 << 3) | (1 << 2) | 2), 365 ((2 << 4) | (0 << 3) | (1 << 2) | 3), 366 ((3 << 4) | (1 << 3) | (1 << 2) | 0), 367 ((3 << 4) | (1 << 3) | (1 << 2) | 1), 368 ((2 << 4) | (1 << 3) | (1 << 2) | 2), 369 ((3 << 4) | (0 << 3) | (0 << 2) | 1), 370 ((2 << 4) | (0 << 3) | (1 << 2) | 1), 371 }; 372 373 u16 ddr4_cfg_2_rbc[] = { 374 /*************************** 375 * [6] cs 0:0cs 1:2 cs 376 * [5:3] row(13+n) 377 * [2] cs(0:0 cs, 1:2 cs) 378 * [1] bw 0: 16bit 1:32bit 379 * [0] diebw 0:8bit 1:16bit 380 ***************************/ 381 /* cs, row, cs, bw, diebw */ 382 ((0 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 0), 383 ((1 << 6) | (2 << 3) | (0 << 2) | (1 << 1) | 0), 384 ((0 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 0), 385 ((1 << 6) | (3 << 3) | (0 << 2) | (0 << 1) | 0), 386 ((0 << 6) | (4 << 3) | (0 << 2) | (1 << 1) | 1), 387 ((1 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 1), 388 ((1 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 1), 389 ((0 << 6) | (2 << 3) | (1 << 2) | (1 << 1) | 0), 390 ((0 << 6) | (3 << 3) | (1 << 2) | (0 << 1) | 0), 391 ((0 << 6) | (3 << 3) | (1 << 2) | (1 << 1) | 1), 392 ((0 << 6) | (4 << 3) | (1 << 2) | (0 << 1) | 1), 393 }; 394 395 u32 addrmap[21][9] = { 396 /* map0 map1 map2 map3 map4 map5 map6 map7 map8 */ 397 {22, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606, 398 0x06060606, 0x00000f0f, 0x3f3f}, 399 {23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, 400 0x07070707, 0x00000f0f, 0x3f3f}, 401 {23, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808, 402 0x0f080808, 0x00000f0f, 0x3f3f}, 403 {24, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808, 404 0x08080808, 0x00000f0f, 0x3f3f}, 405 {24, 0x000a0a0a, 0x00000000, 0x00000000, 0x00000000, 0x09090909, 406 0x0f090909, 0x00000f0f, 0x3f3f}, 407 {6, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x07070707, 408 0x07070707, 0x00000f0f, 0x3f3f}, 409 {7, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x08080808, 410 0x08080808, 0x00000f0f, 0x3f3f}, 411 {8, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x09090909, 412 0x0f090909, 0x00000f0f, 0x3f3f}, 413 {22, 0x001f0808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606, 414 0x06060606, 0x00000f0f, 0x3f3f}, 415 {23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, 416 0x0f070707, 0x00000f0f, 0x3f3f}, 417 418 {24, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, 419 0x08080808, 0x00000f0f, 0x0801}, 420 {23, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, 421 0x0f080808, 0x00000f0f, 0x0801}, 422 {24, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, 423 0x07070707, 0x00000f07, 0x0700}, 424 {23, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, 425 0x07070707, 0x00000f0f, 0x0700}, 426 {24, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, 427 0x07070707, 0x00000f07, 0x3f01}, 428 {23, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, 429 0x07070707, 0x00000f0f, 0x3f01}, 430 {24, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x06060606, 431 0x06060606, 0x00000f06, 0x3f00}, 432 {8, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x09090909, 433 0x0f090909, 0x00000f0f, 0x0801}, 434 {7, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x08080808, 435 0x08080808, 0x00000f0f, 0x0700}, 436 {7, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, 437 0x08080808, 0x00000f0f, 0x3f01}, 438 439 {6, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, 440 0x07070707, 0x00000f07, 0x3f00} 441 }; 442 443 struct rk3328_msch_timings { 444 union noc_ddrtiming ddrtiming; 445 union noc_ddrmode ddrmode; 446 u32 readlatency; 447 union noc_activate activate; 448 union noc_devtodev devtodev; 449 union noc_ddr4timing ddr4timing; 450 u32 agingx0; 451 }; 452 453 struct rk3328_msch_regs { 454 u32 coreid; 455 u32 revisionid; 456 u32 ddrconf; 457 u32 ddrtiming; 458 u32 ddrmode; 459 u32 readlatency; 460 u32 aging0; 461 u32 aging1; 462 u32 aging2; 463 u32 aging3; 464 u32 aging4; 465 u32 aging5; 466 u32 reserved[2]; 467 u32 activate; 468 u32 devtodev; 469 u32 ddr4_timing; 470 }; 471 472 struct rk3328_ddr_grf_regs { 473 u32 ddr_grf_con[4]; 474 u32 reserved[(0x100 - 0x10) / 4]; 475 u32 ddr_grf_status[11]; 476 }; 477 478 struct rk3328_ddr_pctl_regs { 479 u32 pctl[30][2]; 480 }; 481 482 struct rk3328_ddr_phy_regs { 483 u32 phy[5][2]; 484 }; 485 486 struct rk3328_ddr_skew { 487 u32 a0_a1_skew[15]; 488 u32 cs0_dm0_skew[11]; 489 u32 cs0_dm1_skew[11]; 490 u32 cs0_dm2_skew[11]; 491 u32 cs0_dm3_skew[11]; 492 u32 cs1_dm0_skew[11]; 493 u32 cs1_dm1_skew[11]; 494 u32 cs1_dm2_skew[11]; 495 u32 cs1_dm3_skew[11]; 496 }; 497 498 struct rk3328_sdram_channel { 499 unsigned int rank; 500 unsigned int col; 501 /* 3:8bank, 2:4bank */ 502 unsigned int bk; 503 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ 504 unsigned int bw; 505 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ 506 unsigned int dbw; 507 unsigned int row_3_4; 508 unsigned int cs0_row; 509 unsigned int cs1_row; 510 unsigned int ddrconfig; 511 struct rk3328_msch_timings noc_timings; 512 }; 513 514 struct rk3328_sdram_params { 515 struct rk3328_sdram_channel ch; 516 unsigned int ddr_freq; 517 unsigned int dramtype; 518 unsigned int odt; 519 struct rk3328_ddr_pctl_regs pctl_regs; 520 struct rk3328_ddr_phy_regs phy_regs; 521 struct rk3328_ddr_skew skew; 522 }; 523 524 #define PHY_REG(base, n) (base + 4 * (n)) 525 526 #endif 527