1 /* 2 * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARCH_SDRAM_RK3328_H 8 #define _ASM_ARCH_SDRAM_RK3328_H 9 10 enum { 11 DDR4 = 0, 12 DDR3 = 3, 13 LPDDR2 = 5, 14 LPDDR3 = 6, 15 LPDDR4 = 7, 16 UNUSED = 0xFF 17 }; 18 19 #define SR_IDLE 93 20 #define PD_IDLE 13 21 #define SDRAM_ADDR 0x00000000 22 #define PATTERN (0x5aa5f00f) 23 24 /* ddr pctl registers define */ 25 #define DDR_PCTL2_MSTR 0x0 26 #define DDR_PCTL2_STAT 0x4 27 #define DDR_PCTL2_MSTR1 0x8 28 #define DDR_PCTL2_MRCTRL0 0x10 29 #define DDR_PCTL2_MRCTRL1 0x14 30 #define DDR_PCTL2_MRSTAT 0x18 31 #define DDR_PCTL2_MRCTRL2 0x1c 32 #define DDR_PCTL2_DERATEEN 0x20 33 #define DDR_PCTL2_DERATEINT 0x24 34 #define DDR_PCTL2_PWRCTL 0x30 35 #define DDR_PCTL2_PWRTMG 0x34 36 #define DDR_PCTL2_HWLPCTL 0x38 37 #define DDR_PCTL2_RFSHCTL0 0x50 38 #define DDR_PCTL2_RFSHCTL1 0x54 39 #define DDR_PCTL2_RFSHCTL2 0x58 40 #define DDR_PCTL2_RFSHCTL4 0x5c 41 #define DDR_PCTL2_RFSHCTL3 0x60 42 #define DDR_PCTL2_RFSHTMG 0x64 43 #define DDR_PCTL2_RFSHTMG1 0x68 44 #define DDR_PCTL2_RFSHCTL5 0x6c 45 #define DDR_PCTL2_INIT0 0xd0 46 #define DDR_PCTL2_INIT1 0xd4 47 #define DDR_PCTL2_INIT2 0xd8 48 #define DDR_PCTL2_INIT3 0xdc 49 #define DDR_PCTL2_INIT4 0xe0 50 #define DDR_PCTL2_INIT5 0xe4 51 #define DDR_PCTL2_INIT6 0xe8 52 #define DDR_PCTL2_INIT7 0xec 53 #define DDR_PCTL2_DIMMCTL 0xf0 54 #define DDR_PCTL2_RANKCTL 0xf4 55 #define DDR_PCTL2_CHCTL 0xfc 56 #define DDR_PCTL2_DRAMTMG0 0x100 57 #define DDR_PCTL2_DRAMTMG1 0x104 58 #define DDR_PCTL2_DRAMTMG2 0x108 59 #define DDR_PCTL2_DRAMTMG3 0x10c 60 #define DDR_PCTL2_DRAMTMG4 0x110 61 #define DDR_PCTL2_DRAMTMG5 0x114 62 #define DDR_PCTL2_DRAMTMG6 0x118 63 #define DDR_PCTL2_DRAMTMG7 0x11c 64 #define DDR_PCTL2_DRAMTMG8 0x120 65 #define DDR_PCTL2_DRAMTMG9 0x124 66 #define DDR_PCTL2_DRAMTMG10 0x128 67 #define DDR_PCTL2_DRAMTMG11 0x12c 68 #define DDR_PCTL2_DRAMTMG12 0x130 69 #define DDR_PCTL2_DRAMTMG13 0x134 70 #define DDR_PCTL2_DRAMTMG14 0x138 71 #define DDR_PCTL2_DRAMTMG15 0x13c 72 #define DDR_PCTL2_DRAMTMG16 0x140 73 #define DDR_PCTL2_ZQCTL0 0x180 74 #define DDR_PCTL2_ZQCTL1 0x184 75 #define DDR_PCTL2_ZQCTL2 0x188 76 #define DDR_PCTL2_ZQSTAT 0x18c 77 #define DDR_PCTL2_DFITMG0 0x190 78 #define DDR_PCTL2_DFITMG1 0x194 79 #define DDR_PCTL2_DFILPCFG0 0x198 80 #define DDR_PCTL2_DFILPCFG1 0x19c 81 #define DDR_PCTL2_DFIUPD0 0x1a0 82 #define DDR_PCTL2_DFIUPD1 0x1a4 83 #define DDR_PCTL2_DFIUPD2 0x1a8 84 #define DDR_PCTL2_DFIMISC 0x1b0 85 #define DDR_PCTL2_DFITMG2 0x1b4 86 #define DDR_PCTL2_DFITMG3 0x1b8 87 #define DDR_PCTL2_DFISTAT 0x1bc 88 #define DDR_PCTL2_DBICTL 0x1c0 89 #define DDR_PCTL2_ADDRMAP0 0x200 90 #define DDR_PCTL2_ADDRMAP1 0x204 91 #define DDR_PCTL2_ADDRMAP2 0x208 92 #define DDR_PCTL2_ADDRMAP3 0x20c 93 #define DDR_PCTL2_ADDRMAP4 0x210 94 #define DDR_PCTL2_ADDRMAP5 0x214 95 #define DDR_PCTL2_ADDRMAP6 0x218 96 #define DDR_PCTL2_ADDRMAP7 0x21c 97 #define DDR_PCTL2_ADDRMAP8 0x220 98 #define DDR_PCTL2_ADDRMAP9 0x224 99 #define DDR_PCTL2_ADDRMAP10 0x228 100 #define DDR_PCTL2_ADDRMAP11 0x22c 101 #define DDR_PCTL2_ODTCFG 0x240 102 #define DDR_PCTL2_ODTMAP 0x244 103 #define DDR_PCTL2_SCHED 0x250 104 #define DDR_PCTL2_SCHED1 0x254 105 #define DDR_PCTL2_PERFHPR1 0x25c 106 #define DDR_PCTL2_PERFLPR1 0x264 107 #define DDR_PCTL2_PERFWR1 0x26c 108 #define DDR_PCTL2_DQMAP0 0x280 109 #define DDR_PCTL2_DQMAP1 0x284 110 #define DDR_PCTL2_DQMAP2 0x288 111 #define DDR_PCTL2_DQMAP3 0x28c 112 #define DDR_PCTL2_DQMAP4 0x290 113 #define DDR_PCTL2_DQMAP5 0x294 114 #define DDR_PCTL2_DBG0 0x300 115 #define DDR_PCTL2_DBG1 0x304 116 #define DDR_PCTL2_DBGCAM 0x308 117 #define DDR_PCTL2_DBGCMD 0x30c 118 #define DDR_PCTL2_DBGSTAT 0x310 119 #define DDR_PCTL2_SWCTL 0x320 120 #define DDR_PCTL2_SWSTAT 0x324 121 #define DDR_PCTL2_POISONCFG 0x36c 122 #define DDR_PCTL2_POISONSTAT 0x370 123 #define DDR_PCTL2_ADVECCINDEX 0x374 124 #define DDR_PCTL2_ADVECCSTAT 0x378 125 #define DDR_PCTL2_PSTAT 0x3fc 126 #define DDR_PCTL2_PCCFG 0x400 127 #define DDR_PCTL2_PCFGR_n 0x404 128 #define DDR_PCTL2_PCFGW_n 0x408 129 #define DDR_PCTL2_PCTRL_n 0x490 130 131 /* PCTL2_MRSTAT */ 132 #define MR_WR_BUSY BIT(0) 133 134 /* PHY_REG0 */ 135 #define DIGITAL_DERESET BIT(3) 136 #define ANALOG_DERESET BIT(2) 137 #define DIGITAL_RESET (0 << 3) 138 #define ANALOG_RESET (0 << 2) 139 140 /* PHY_REG1 */ 141 #define PHY_DDR2 (0) 142 #define PHY_LPDDR2 (1) 143 #define PHY_DDR3 (2) 144 #define PHY_LPDDR3 (3) 145 #define PHY_DDR4 (4) 146 #define PHY_BL_4 (0 << 2) 147 #define PHY_BL_8 BIT(2) 148 149 /* PHY_REG2 */ 150 #define PHY_DTT_EN BIT(0) 151 #define PHY_DTT_DISB (0 << 0) 152 #define PHY_WRITE_LEVELING_EN BIT(2) 153 #define PHY_WRITE_LEVELING_DISB (0 << 2) 154 #define PHY_SELECT_CS0 (2) 155 #define PHY_SELECT_CS1 (1) 156 #define PHY_SELECT_CS0_1 (0) 157 #define PHY_WRITE_LEVELING_SELECTCS(n) (n << 6) 158 #define PHY_DATA_TRAINING_SELECTCS(n) (n << 4) 159 160 #define PHY_DDR3_RON_RTT_DISABLE (0) 161 #define PHY_DDR3_RON_RTT_451ohm (1) 162 #define PHY_DDR3_RON_RTT_225ohm (2) 163 #define PHY_DDR3_RON_RTT_150ohm (3) 164 #define PHY_DDR3_RON_RTT_112ohm (4) 165 #define PHY_DDR3_RON_RTT_90ohm (5) 166 #define PHY_DDR3_RON_RTT_75ohm (6) 167 #define PHY_DDR3_RON_RTT_64ohm (7) 168 #define PHY_DDR3_RON_RTT_56ohm (16) 169 #define PHY_DDR3_RON_RTT_50ohm (17) 170 #define PHY_DDR3_RON_RTT_45ohm (18) 171 #define PHY_DDR3_RON_RTT_41ohm (19) 172 #define PHY_DDR3_RON_RTT_37ohm (20) 173 #define PHY_DDR3_RON_RTT_34ohm (21) 174 #define PHY_DDR3_RON_RTT_33ohm (22) 175 #define PHY_DDR3_RON_RTT_30ohm (23) 176 #define PHY_DDR3_RON_RTT_28ohm (24) 177 #define PHY_DDR3_RON_RTT_26ohm (25) 178 #define PHY_DDR3_RON_RTT_25ohm (26) 179 #define PHY_DDR3_RON_RTT_23ohm (27) 180 #define PHY_DDR3_RON_RTT_22ohm (28) 181 #define PHY_DDR3_RON_RTT_21ohm (29) 182 #define PHY_DDR3_RON_RTT_20ohm (30) 183 #define PHY_DDR3_RON_RTT_19ohm (31) 184 185 #define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0) 186 #define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1) 187 #define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2) 188 #define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3) 189 #define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4) 190 #define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5) 191 #define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6) 192 #define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7) 193 #define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16) 194 #define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17) 195 #define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18) 196 #define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19) 197 #define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20) 198 #define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21) 199 #define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22) 200 #define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23) 201 #define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24) 202 #define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25) 203 #define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26) 204 #define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27) 205 #define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28) 206 #define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29) 207 #define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30) 208 #define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31) 209 210 /* noc registers define */ 211 #define DDRCONF 0x8 212 #define DDRTIMING 0xc 213 #define DDRMODE 0x10 214 #define READLATENCY 0x14 215 #define AGING0 0x18 216 #define AGING1 0x1c 217 #define AGING2 0x20 218 #define AGING3 0x24 219 #define AGING4 0x28 220 #define AGING5 0x2c 221 #define ACTIVATE 0x38 222 #define DEVTODEV 0x3c 223 #define DDR4TIMING 0x40 224 225 /* DDR GRF */ 226 #define DDR_GRF_CON(n) (0 + (n) * 4) 227 #define DDR_GRF_STATUS_BASE (0X100) 228 #define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) 229 230 /* 231 * sys_reg bitfield struct 232 * [31] row_3_4_ch1 233 * [30] row_3_4_ch0 234 * [29:28] chinfo 235 * [27] rank_ch1 236 * [26:25] col_ch1 237 * [24] bk_ch1 238 * [23:22] cs0_row_ch1 239 * [21:20] cs1_row_ch1 240 * [19:18] bw_ch1 241 * [17:16] dbw_ch1; 242 * [15:13] ddrtype 243 * [12] channelnum 244 * [11] rank_ch0 245 * [10:9] col_ch0 246 * [8] bk_ch0 247 * [7:6] cs0_row_ch0 248 * [5:4] cs1_row_ch0 249 * [3:2] bw_ch0 250 * [1:0] dbw_ch0 251 */ 252 #define SYS_REG_ENC_ROW_3_4(n) ((n) << 30) 253 #define SYS_REG_DEC_ROW_3_4(n) ((n >> 30) & 0x1) 254 #define SYS_REG_ENC_CHINFO() (1 << 28) 255 #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) 256 #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) 257 #define SYS_REG_DEC_NUM_CH(n) (1 + ((n >> 12) & 0x1)) 258 #define SYS_REG_ENC_RANK(n) (((n) - 1) << 11) 259 #define SYS_REG_DEC_RANK(n) (1 + ((n >> 11) & 0x1)) 260 #define SYS_REG_ENC_COL(n) (((n) - 9) << 9) 261 #define SYS_REG_DEC_COL(n) (9 + ((n >> 9) & 0x3)) 262 #define SYS_REG_ENC_BK(n) (((n) == 3 ? 0 : 1) << 8) 263 #define SYS_REG_DEC_BK(n) (3 - ((n >> 8) & 0x1)) 264 #define SYS_REG_ENC_CS0_ROW(n) (((n) - 13) << 6) 265 #define SYS_REG_DEC_CS0_ROW(n) (13 + ((n >> 6) & 0x3)) 266 #define SYS_REG_ENC_CS1_ROW(n) (((n) - 13) << 4) 267 #define SYS_REG_DEC_CS1_ROW(n) (13 + ((n >> 4) & 0x3)) 268 #define SYS_REG_ENC_BW(n) ((2 >> (n)) << 2) 269 #define SYS_REG_DEC_BW(n) (2 >> ((n >> 2) & 0x3)) 270 #define SYS_REG_ENC_DBW(n) ((2 >> (n)) << 0) 271 #define SYS_REG_DEC_DBW(n) (2 >> ((n >> 0) & 0x3)) 272 273 /* CRU_SOFTRESET_CON5 */ 274 #define ddrphy_psrstn_req(n) (((0x1 << 15) << 16) | (n << 15)) 275 #define ddrphy_srstn_req(n) (((0x1 << 14) << 16) | (n << 14)) 276 #define ddrctrl_psrstn_req(n) (((0x1 << 13) << 16) | (n << 13)) 277 #define ddrctrl_srstn_req(n) (((0x1 << 12) << 16) | (n << 12)) 278 #define ddrmsch_srstn_req(n) (((0x1 << 11) << 16) | (n << 11)) 279 #define msch_srstn_req(n) (((0x1 << 9) << 16) | (n << 9)) 280 #define dfimon_srstn_req(n) (((0x1 << 8) << 16) | (n << 8)) 281 #define grf_ddr_srstn_req(n) (((0x1 << 7) << 16) | (n << 7)) 282 /* CRU_SOFTRESET_CON9 */ 283 #define ddrctrl_asrstn_req(n) (((0x1 << 9) << 16) | (n << 9)) 284 285 /* CRU register */ 286 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) 287 #define CRU_MODE (0x80) 288 #define CRU_GLB_CNT_TH (0x90) 289 #define CRU_CLKSEL_CON_BASE 0x100 290 #define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON_BASE + ((i) * 4)) 291 #define CRU_CLKGATE_CON_BASE 0x200 292 #define CRU_CLKGATE_CON(i) (CRU_CLKGATE_CON_BASE + ((i) * 4)) 293 #define CRU_CLKSFTRST_CON_BASE 0x300 294 #define CRU_CLKSFTRST_CON(i) (CRU_CLKSFTRST_CON_BASE + ((i) * 4)) 295 296 /* CRU_PLL_CON0 */ 297 #define PB(n) ((0x1 << (15 + 16)) | ((n) << 15)) 298 #define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12)) 299 #define FBDIV(n) ((0xFFF << 16) | (n)) 300 301 /* CRU_PLL_CON1 */ 302 #define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15)) 303 #define RST(n) ((0x1 << (14 + 16)) | ((n) << 14)) 304 #define PD(n) ((0x1 << (13 + 16)) | ((n) << 13)) 305 #define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12)) 306 #define LOCK(n) (((n) >> 10) & 0x1) 307 #define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6)) 308 #define REFDIV(n) ((0x3F << 16) | (n)) 309 310 union noc_ddrtiming { 311 u32 d32; 312 struct { 313 unsigned acttoact:6; 314 unsigned rdtomiss:6; 315 unsigned wrtomiss:6; 316 unsigned burstlen:3; 317 unsigned rdtowr:5; 318 unsigned wrtord:5; 319 unsigned bwratio:1; 320 } b; 321 } NOC_TIMING_T; 322 323 union noc_activate { 324 u32 d32; 325 struct { 326 unsigned rrd:4; 327 unsigned faw:6; 328 unsigned fawbank:1; 329 unsigned reserved1:21; 330 } b; 331 }; 332 333 union noc_devtodev { 334 u32 d32; 335 struct { 336 unsigned busrdtord:2; 337 unsigned busrdtowr:2; 338 unsigned buswrtord:2; 339 unsigned reserved2:26; 340 } b; 341 }; 342 343 union noc_ddr4timing { 344 u32 d32; 345 struct { 346 unsigned ccdl:3; 347 unsigned wrtordl:5; 348 unsigned rrdl:4; 349 unsigned reserved2:20; 350 } b; 351 }; 352 353 union noc_ddrmode { 354 u32 d32; 355 struct { 356 unsigned autoprecharge:1; 357 unsigned bwratioextended:1; 358 unsigned reserved3:30; 359 } b; 360 }; 361 362 u16 ddr_cfg_2_rbc[] = { 363 /*************************** 364 * [5:4] row(13+n) 365 * [3] cs(0:0 cs, 1:2 cs) 366 * [2] bank(0:0bank,1:8bank) 367 * [1:0] col(11+n) 368 ****************************/ 369 /* row, cs, bank, col */ 370 ((3 << 4) | (0 << 3) | (1 << 2) | 0), 371 ((3 << 4) | (0 << 3) | (1 << 2) | 1), 372 ((2 << 4) | (0 << 3) | (1 << 2) | 2), 373 ((3 << 4) | (0 << 3) | (1 << 2) | 2), 374 ((2 << 4) | (0 << 3) | (1 << 2) | 3), 375 ((3 << 4) | (1 << 3) | (1 << 2) | 0), 376 ((3 << 4) | (1 << 3) | (1 << 2) | 1), 377 ((2 << 4) | (1 << 3) | (1 << 2) | 2), 378 ((3 << 4) | (0 << 3) | (0 << 2) | 1), 379 ((2 << 4) | (0 << 3) | (1 << 2) | 1), 380 }; 381 382 u16 ddr4_cfg_2_rbc[] = { 383 /*************************** 384 * [6] cs 0:0cs 1:2 cs 385 * [5:3] row(13+n) 386 * [2] cs(0:0 cs, 1:2 cs) 387 * [1] bw 0: 16bit 1:32bit 388 * [0] diebw 0:8bit 1:16bit 389 ***************************/ 390 /* cs, row, cs, bw, diebw */ 391 ((0 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 0), 392 ((1 << 6) | (2 << 3) | (0 << 2) | (1 << 1) | 0), 393 ((0 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 0), 394 ((1 << 6) | (3 << 3) | (0 << 2) | (0 << 1) | 0), 395 ((0 << 6) | (4 << 3) | (0 << 2) | (1 << 1) | 1), 396 ((1 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 1), 397 ((1 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 1), 398 ((0 << 6) | (2 << 3) | (1 << 2) | (1 << 1) | 0), 399 ((0 << 6) | (3 << 3) | (1 << 2) | (0 << 1) | 0), 400 ((0 << 6) | (3 << 3) | (1 << 2) | (1 << 1) | 1), 401 ((0 << 6) | (4 << 3) | (1 << 2) | (0 << 1) | 1), 402 }; 403 404 u32 addrmap[21][9] = { 405 /* map0 map1 map2 map3 map4 map5 map6 map7 map8 */ 406 {22, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606, 407 0x06060606, 0x00000f0f, 0x3f3f}, 408 {23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, 409 0x07070707, 0x00000f0f, 0x3f3f}, 410 {23, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808, 411 0x0f080808, 0x00000f0f, 0x3f3f}, 412 {24, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808, 413 0x08080808, 0x00000f0f, 0x3f3f}, 414 {24, 0x000a0a0a, 0x00000000, 0x00000000, 0x00000000, 0x09090909, 415 0x0f090909, 0x00000f0f, 0x3f3f}, 416 {6, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x07070707, 417 0x07070707, 0x00000f0f, 0x3f3f}, 418 {7, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x08080808, 419 0x08080808, 0x00000f0f, 0x3f3f}, 420 {8, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x09090909, 421 0x0f090909, 0x00000f0f, 0x3f3f}, 422 {22, 0x001f0808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606, 423 0x06060606, 0x00000f0f, 0x3f3f}, 424 {23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, 425 0x0f070707, 0x00000f0f, 0x3f3f}, 426 427 {24, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, 428 0x08080808, 0x00000f0f, 0x0801}, 429 {23, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, 430 0x0f080808, 0x00000f0f, 0x0801}, 431 {24, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, 432 0x07070707, 0x00000f07, 0x0700}, 433 {23, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, 434 0x07070707, 0x00000f0f, 0x0700}, 435 {24, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, 436 0x07070707, 0x00000f07, 0x3f01}, 437 {23, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, 438 0x07070707, 0x00000f0f, 0x3f01}, 439 {24, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x06060606, 440 0x06060606, 0x00000f06, 0x3f00}, 441 {8, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x09090909, 442 0x0f090909, 0x00000f0f, 0x0801}, 443 {7, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x08080808, 444 0x08080808, 0x00000f0f, 0x0700}, 445 {7, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, 446 0x08080808, 0x00000f0f, 0x3f01}, 447 448 {6, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, 449 0x07070707, 0x00000f07, 0x3f00} 450 }; 451 452 struct rk3328_msch_timings { 453 union noc_ddrtiming ddrtiming; 454 union noc_ddrmode ddrmode; 455 u32 readlatency; 456 union noc_activate activate; 457 union noc_devtodev devtodev; 458 union noc_ddr4timing ddr4timing; 459 u32 agingx0; 460 }; 461 462 struct rk3328_msch_regs { 463 u32 coreid; 464 u32 revisionid; 465 u32 ddrconf; 466 u32 ddrtiming; 467 u32 ddrmode; 468 u32 readlatency; 469 u32 aging0; 470 u32 aging1; 471 u32 aging2; 472 u32 aging3; 473 u32 aging4; 474 u32 aging5; 475 u32 reserved[2]; 476 u32 activate; 477 u32 devtodev; 478 u32 ddr4_timing; 479 }; 480 481 struct rk3328_ddr_grf_regs { 482 u32 ddr_grf_con[4]; 483 u32 reserved[(0x100 - 0x10) / 4]; 484 u32 ddr_grf_status[11]; 485 }; 486 487 struct rk3328_ddr_pctl_regs { 488 u32 pctl[30][2]; 489 }; 490 491 struct rk3328_ddr_phy_regs { 492 u32 phy[5][2]; 493 }; 494 495 struct rk3328_ddr_skew { 496 u32 a0_a1_skew[15]; 497 u32 cs0_dm0_skew[11]; 498 u32 cs0_dm1_skew[11]; 499 u32 cs0_dm2_skew[11]; 500 u32 cs0_dm3_skew[11]; 501 u32 cs1_dm0_skew[11]; 502 u32 cs1_dm1_skew[11]; 503 u32 cs1_dm2_skew[11]; 504 u32 cs1_dm3_skew[11]; 505 }; 506 507 struct rk3328_sdram_channel { 508 unsigned int rank; 509 unsigned int col; 510 /* 3:8bank, 2:4bank */ 511 unsigned int bk; 512 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ 513 unsigned int bw; 514 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ 515 unsigned int dbw; 516 unsigned int row_3_4; 517 unsigned int cs0_row; 518 unsigned int cs1_row; 519 unsigned int ddrconfig; 520 struct rk3328_msch_timings noc_timings; 521 }; 522 523 struct rk3328_sdram_params { 524 struct rk3328_sdram_channel ch; 525 unsigned int ddr_freq; 526 unsigned int dramtype; 527 unsigned int odt; 528 struct rk3328_ddr_pctl_regs pctl_regs; 529 struct rk3328_ddr_phy_regs phy_regs; 530 struct rk3328_ddr_skew skew; 531 }; 532 533 #define PHY_REG(base, n) (base + 4 * (n)) 534 535 #endif 536