1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2018 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ASM_ARCH_SDRAM_PX30_H 7 #define _ASM_ARCH_SDRAM_PX30_H 8 #include <asm/arch/sdram_share.h> 9 #include <asm/arch/sdram_pctl_px30.h> 10 #include <asm/arch/sdram_phy_px30.h> 11 #include <asm/arch/sdram_phy_ron_rtt_px30.h> 12 13 #define SR_IDLE 93 14 #define PD_IDLE 13 15 16 /* PMUGRF */ 17 #define PMUGRF_OS_REG0 (0x200) 18 #define PMUGRF_OS_REG(n) (PMUGRF_OS_REG0 + (n) * 4) 19 20 /* DDR GRF */ 21 #define DDR_GRF_CON(n) (0 + (n) * 4) 22 #define DDR_GRF_STATUS_BASE (0X100) 23 #define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) 24 #define DDR_GRF_LP_CON (0x20) 25 26 #define SPLIT_MODE_32_L16_VALID (0) 27 #define SPLIT_MODE_32_H16_VALID (1) 28 #define SPLIT_MODE_16_L8_VALID (2) 29 #define SPLIT_MODE_16_H8_VALID (3) 30 31 #define DDR_GRF_SPLIT_CON (0x8) 32 #define SPLIT_MODE_MASK (0x3) 33 #define SPLIT_MODE_OFFSET (9) 34 #define SPLIT_BYPASS_MASK (1) 35 #define SPLIT_BYPASS_OFFSET (8) 36 #define SPLIT_SIZE_MASK (0xff) 37 #define SPLIT_SIZE_OFFSET (0) 38 39 /* CRU define */ 40 /* CRU_PLL_CON0 */ 41 #define PB(n) ((0x1 << (15 + 16)) | ((n) << 15)) 42 #define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12)) 43 #define FBDIV(n) ((0xFFF << 16) | (n)) 44 45 /* CRU_PLL_CON1 */ 46 #define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15)) 47 #define RST(n) ((0x1 << (14 + 16)) | ((n) << 14)) 48 #define PD(n) ((0x1 << (13 + 16)) | ((n) << 13)) 49 #define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12)) 50 #define LOCK(n) (((n) >> 10) & 0x1) 51 #define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6)) 52 #define REFDIV(n) ((0x3F << 16) | (n)) 53 54 /* CRU_MODE */ 55 #define CLOCK_FROM_XIN_OSC (0) 56 #define CLOCK_FROM_PLL (1) 57 #define CLOCK_FROM_RTC_32K (2) 58 #define DPLL_MODE(n) ((0x3 << (4 + 16)) | ((n) << 4)) 59 60 /* CRU_SOFTRESET_CON1 */ 61 #define upctl2_psrstn_req(n) (((0x1 << 6) << 16) | ((n) << 6)) 62 #define upctl2_asrstn_req(n) (((0x1 << 5) << 16) | ((n) << 5)) 63 #define upctl2_srstn_req(n) (((0x1 << 4) << 16) | ((n) << 4)) 64 65 /* CRU_SOFTRESET_CON2 */ 66 #define ddrphy_psrstn_req(n) (((0x1 << 2) << 16) | ((n) << 2)) 67 #define ddrphy_srstn_req(n) (((0x1 << 0) << 16) | ((n) << 0)) 68 69 /* CRU register */ 70 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) 71 #define CRU_MODE (0xa0) 72 #define CRU_GLB_CNT_TH (0xb0) 73 #define CRU_CLKSEL_CON_BASE 0x100 74 #define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON_BASE + ((i) * 4)) 75 #define CRU_CLKGATE_CON_BASE 0x200 76 #define CRU_CLKGATE_CON(i) (CRU_CLKGATE_CON_BASE + ((i) * 4)) 77 #define CRU_CLKSFTRST_CON_BASE 0x300 78 #define CRU_CLKSFTRST_CON(i) (CRU_CLKSFTRST_CON_BASE + ((i) * 4)) 79 80 u8 ddr_cfg_2_rbc[] = { 81 /* 82 * [6:4] max row: 13+n 83 * [3] bank(0:4bank,1:8bank) 84 * [2:0] col(10+n) 85 */ 86 ((5 << 4) | (1 << 3) | 0), /* 0 */ 87 ((5 << 4) | (1 << 3) | 1), /* 1 */ 88 ((4 << 4) | (1 << 3) | 2), /* 2 */ 89 ((3 << 4) | (1 << 3) | 3), /* 3 */ 90 ((2 << 4) | (1 << 3) | 4), /* 4 */ 91 ((5 << 4) | (0 << 3) | 2), /* 5 */ 92 ((4 << 4) | (1 << 3) | 2), /* 6 */ 93 /*((0<<3)|3),*/ /* 12 for ddr4 */ 94 /*((1<<3)|1),*/ /* 13 B,C exchange for rkvdec */ 95 }; 96 97 /* 98 * for ddr4 if ddrconfig=7, upctl should set 7 and noc should 99 * set to 1 for more efficient. 100 * noc ddrconf, upctl addrmap 101 * 1 7 102 * 2 8 103 * 3 9 104 * 12 10 105 * 5 11 106 */ 107 u8 d4_rbc_2_d3_rbc[] = { 108 1, /* 7 */ 109 2, /* 8 */ 110 3, /* 9 */ 111 12, /* 10 */ 112 5, /* 11 */ 113 }; 114 115 /* 116 * row higher than cs should be disabled by set to 0xf 117 * rank addrmap calculate by real cap. 118 */ 119 u32 addrmap[][8] = { 120 /* map0 map1, map2, map3, map4, map5 121 * map6, map7, map8 122 * ------------------------------------------------------- 123 * bk2-0 col 5-2 col 9-6 col 11-10 row 11-0 124 * row 15-12 row 17-16 bg1,0 125 * ------------------------------------------------------- 126 * 4,3,2 5-2 9-6 6 127 * 3,2 128 */ 129 {0x00060606, 0x00000000, 0x1f1f0000, 0x00001f1f, 0x05050505, 130 0x05050505, 0x00000505, 0x3f3f}, /* 0 */ 131 {0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606, 132 0x06060606, 0x06060606, 0x3f3f}, /* 1 */ 133 {0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, 134 0x07070707, 0x00000f07, 0x3f3f}, /* 2 */ 135 {0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808, 136 0x08080808, 0x00000f0f, 0x3f3f}, /* 3 */ 137 {0x000a0a0a, 0x00000000, 0x00000000, 0x00000000, 0x09090909, 138 0x0f090909, 0x00000f0f, 0x3f3f}, /* 4 */ 139 {0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606, 140 0x06060606, 0x00000606, 0x3f3f}, /* 5 */ 141 {0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, 142 0x07070707, 0x00000f0f, 0x3f3f}, /* 6 */ 143 {0x003f0808, 0x00000006, 0x1f1f0000, 0x00001f1f, 0x06060606, 144 0x06060606, 0x00000606, 0x0600}, /* 7 */ 145 {0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, 146 0x07070707, 0x00000f07, 0x0700}, /* 8 */ 147 {0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, 148 0x08080808, 0x00000f0f, 0x0801}, /* 9 */ 149 {0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, 150 0x07070707, 0x00000f07, 0x3f01}, /* 10 */ 151 {0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x06060606, 152 0x06060606, 0x00000606, 0x3f00}, /* 11 */ 153 /* when ddr4 12 map to 10, when ddr3 12 unused */ 154 {0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, 155 0x07070707, 0x00000f07, 0x3f01}, /* 10 */ 156 {0x00070706, 0x00000000, 0x1f010000, 0x00001f1f, 0x06060606, 157 0x06060606, 0x00000606, 0x3f3f}, /* 13 */ 158 }; 159 160 struct px30_ddr_grf_regs { 161 u32 ddr_grf_con[4]; 162 u32 reserved1[(0x20 - 0x10) / 4]; 163 u32 ddr_grf_lp_con; 164 u32 reserved2[(0x100 - 0x24) / 4]; 165 u32 ddr_grf_status[11]; 166 }; 167 168 struct px30_sdram_channel { 169 struct sdram_cap_info cap_info; 170 struct sdram_msch_timings noc_timings; 171 }; 172 173 struct px30_sdram_params { 174 struct px30_sdram_channel ch; 175 struct sdram_base_params base; 176 struct ddr_pctl_regs pctl_regs; 177 struct ddr_phy_regs phy_regs; 178 struct ddr_phy_skew *skew; 179 }; 180 #endif 181