1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2018 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ASM_ARCH_SDRAM_PX30_H 7 #define _ASM_ARCH_SDRAM_PX30_H 8 9 #define SR_IDLE 93 10 #define PD_IDLE 13 11 #define PATTERN (0x5aa5f00f) 12 13 /* ddr pctl registers define */ 14 #define DDR_PCTL2_MSTR 0x0 15 #define DDR_PCTL2_STAT 0x4 16 #define DDR_PCTL2_MSTR1 0x8 17 #define DDR_PCTL2_MRCTRL0 0x10 18 #define DDR_PCTL2_MRCTRL1 0x14 19 #define DDR_PCTL2_MRSTAT 0x18 20 #define DDR_PCTL2_MRCTRL2 0x1c 21 #define DDR_PCTL2_DERATEEN 0x20 22 #define DDR_PCTL2_DERATEINT 0x24 23 #define DDR_PCTL2_PWRCTL 0x30 24 #define DDR_PCTL2_PWRTMG 0x34 25 #define DDR_PCTL2_HWLPCTL 0x38 26 #define DDR_PCTL2_RFSHCTL0 0x50 27 #define DDR_PCTL2_RFSHCTL1 0x54 28 #define DDR_PCTL2_RFSHCTL2 0x58 29 #define DDR_PCTL2_RFSHCTL4 0x5c 30 #define DDR_PCTL2_RFSHCTL3 0x60 31 #define DDR_PCTL2_RFSHTMG 0x64 32 #define DDR_PCTL2_RFSHTMG1 0x68 33 #define DDR_PCTL2_RFSHCTL5 0x6c 34 #define DDR_PCTL2_INIT0 0xd0 35 #define DDR_PCTL2_INIT1 0xd4 36 #define DDR_PCTL2_INIT2 0xd8 37 #define DDR_PCTL2_INIT3 0xdc 38 #define DDR_PCTL2_INIT4 0xe0 39 #define DDR_PCTL2_INIT5 0xe4 40 #define DDR_PCTL2_INIT6 0xe8 41 #define DDR_PCTL2_INIT7 0xec 42 #define DDR_PCTL2_DIMMCTL 0xf0 43 #define DDR_PCTL2_RANKCTL 0xf4 44 #define DDR_PCTL2_CHCTL 0xfc 45 #define DDR_PCTL2_DRAMTMG0 0x100 46 #define DDR_PCTL2_DRAMTMG1 0x104 47 #define DDR_PCTL2_DRAMTMG2 0x108 48 #define DDR_PCTL2_DRAMTMG3 0x10c 49 #define DDR_PCTL2_DRAMTMG4 0x110 50 #define DDR_PCTL2_DRAMTMG5 0x114 51 #define DDR_PCTL2_DRAMTMG6 0x118 52 #define DDR_PCTL2_DRAMTMG7 0x11c 53 #define DDR_PCTL2_DRAMTMG8 0x120 54 #define DDR_PCTL2_DRAMTMG9 0x124 55 #define DDR_PCTL2_DRAMTMG10 0x128 56 #define DDR_PCTL2_DRAMTMG11 0x12c 57 #define DDR_PCTL2_DRAMTMG12 0x130 58 #define DDR_PCTL2_DRAMTMG13 0x134 59 #define DDR_PCTL2_DRAMTMG14 0x138 60 #define DDR_PCTL2_DRAMTMG15 0x13c 61 #define DDR_PCTL2_DRAMTMG16 0x140 62 #define DDR_PCTL2_ZQCTL0 0x180 63 #define DDR_PCTL2_ZQCTL1 0x184 64 #define DDR_PCTL2_ZQCTL2 0x188 65 #define DDR_PCTL2_ZQSTAT 0x18c 66 #define DDR_PCTL2_DFITMG0 0x190 67 #define DDR_PCTL2_DFITMG1 0x194 68 #define DDR_PCTL2_DFILPCFG0 0x198 69 #define DDR_PCTL2_DFILPCFG1 0x19c 70 #define DDR_PCTL2_DFIUPD0 0x1a0 71 #define DDR_PCTL2_DFIUPD1 0x1a4 72 #define DDR_PCTL2_DFIUPD2 0x1a8 73 #define DDR_PCTL2_DFIMISC 0x1b0 74 #define DDR_PCTL2_DFITMG2 0x1b4 75 #define DDR_PCTL2_DFITMG3 0x1b8 76 #define DDR_PCTL2_DFISTAT 0x1bc 77 #define DDR_PCTL2_DBICTL 0x1c0 78 #define DDR_PCTL2_ADDRMAP0 0x200 79 #define DDR_PCTL2_ADDRMAP1 0x204 80 #define DDR_PCTL2_ADDRMAP2 0x208 81 #define DDR_PCTL2_ADDRMAP3 0x20c 82 #define DDR_PCTL2_ADDRMAP4 0x210 83 #define DDR_PCTL2_ADDRMAP5 0x214 84 #define DDR_PCTL2_ADDRMAP6 0x218 85 #define DDR_PCTL2_ADDRMAP7 0x21c 86 #define DDR_PCTL2_ADDRMAP8 0x220 87 #define DDR_PCTL2_ADDRMAP9 0x224 88 #define DDR_PCTL2_ADDRMAP10 0x228 89 #define DDR_PCTL2_ADDRMAP11 0x22c 90 #define DDR_PCTL2_ODTCFG 0x240 91 #define DDR_PCTL2_ODTMAP 0x244 92 #define DDR_PCTL2_SCHED 0x250 93 #define DDR_PCTL2_SCHED1 0x254 94 #define DDR_PCTL2_PERFHPR1 0x25c 95 #define DDR_PCTL2_PERFLPR1 0x264 96 #define DDR_PCTL2_PERFWR1 0x26c 97 #define DDR_PCTL2_DQMAP0 0x280 98 #define DDR_PCTL2_DQMAP1 0x284 99 #define DDR_PCTL2_DQMAP2 0x288 100 #define DDR_PCTL2_DQMAP3 0x28c 101 #define DDR_PCTL2_DQMAP4 0x290 102 #define DDR_PCTL2_DQMAP5 0x294 103 #define DDR_PCTL2_DBG0 0x300 104 #define DDR_PCTL2_DBG1 0x304 105 #define DDR_PCTL2_DBGCAM 0x308 106 #define DDR_PCTL2_DBGCMD 0x30c 107 #define DDR_PCTL2_DBGSTAT 0x310 108 #define DDR_PCTL2_SWCTL 0x320 109 #define DDR_PCTL2_SWSTAT 0x324 110 #define DDR_PCTL2_POISONCFG 0x36c 111 #define DDR_PCTL2_POISONSTAT 0x370 112 #define DDR_PCTL2_ADVECCINDEX 0x374 113 #define DDR_PCTL2_ADVECCSTAT 0x378 114 #define DDR_PCTL2_PSTAT 0x3fc 115 #define DDR_PCTL2_PCCFG 0x400 116 #define DDR_PCTL2_PCFGR_n 0x404 117 #define DDR_PCTL2_PCFGW_n 0x408 118 #define DDR_PCTL2_PCTRL_n 0x490 119 120 /* PCTL2_MRSTAT */ 121 #define MR_WR_BUSY BIT(0) 122 123 /* PHY_REG0 */ 124 #define DIGITAL_DERESET BIT(3) 125 #define ANALOG_DERESET BIT(2) 126 #define DIGITAL_RESET (0 << 3) 127 #define ANALOG_RESET (0 << 2) 128 129 /* PHY_REG1 */ 130 #define PHY_DDR2 (0) 131 #define PHY_LPDDR2 (1) 132 #define PHY_DDR3 (2) 133 #define PHY_LPDDR3 (3) 134 #define PHY_DDR4 (4) 135 #define PHY_BL_4 (0 << 2) 136 #define PHY_BL_8 BIT(2) 137 138 /* PHY_REG2 */ 139 #define PHY_DTT_EN BIT(0) 140 #define PHY_DTT_DISB (0 << 0) 141 #define PHY_WRITE_LEVELING_EN BIT(2) 142 #define PHY_WRITE_LEVELING_DISB (0 << 2) 143 #define PHY_SELECT_CS0 (2) 144 #define PHY_SELECT_CS1 (1) 145 #define PHY_SELECT_CS0_1 (0) 146 #define PHY_WRITE_LEVELING_SELECTCS(n) ((n) << 6) 147 #define PHY_DATA_TRAINING_SELECTCS(n) ((n) << 4) 148 149 #define PHY_DDR3_RON_RTT_DISABLE (0) 150 #define PHY_DDR3_RON_RTT_451ohm (1) 151 #define PHY_DDR3_RON_RTT_225ohm (2) 152 #define PHY_DDR3_RON_RTT_150ohm (3) 153 #define PHY_DDR3_RON_RTT_112ohm (4) 154 #define PHY_DDR3_RON_RTT_90ohm (5) 155 #define PHY_DDR3_RON_RTT_75ohm (6) 156 #define PHY_DDR3_RON_RTT_64ohm (7) 157 #define PHY_DDR3_RON_RTT_56ohm (16) 158 #define PHY_DDR3_RON_RTT_50ohm (17) 159 #define PHY_DDR3_RON_RTT_45ohm (18) 160 #define PHY_DDR3_RON_RTT_41ohm (19) 161 #define PHY_DDR3_RON_RTT_37ohm (20) 162 #define PHY_DDR3_RON_RTT_34ohm (21) 163 #define PHY_DDR3_RON_RTT_33ohm (22) 164 #define PHY_DDR3_RON_RTT_30ohm (23) 165 #define PHY_DDR3_RON_RTT_28ohm (24) 166 #define PHY_DDR3_RON_RTT_26ohm (25) 167 #define PHY_DDR3_RON_RTT_25ohm (26) 168 #define PHY_DDR3_RON_RTT_23ohm (27) 169 #define PHY_DDR3_RON_RTT_22ohm (28) 170 #define PHY_DDR3_RON_RTT_21ohm (29) 171 #define PHY_DDR3_RON_RTT_20ohm (30) 172 #define PHY_DDR3_RON_RTT_19ohm (31) 173 174 #define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0) 175 #define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1) 176 #define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2) 177 #define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3) 178 #define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4) 179 #define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5) 180 #define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6) 181 #define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7) 182 #define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16) 183 #define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17) 184 #define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18) 185 #define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19) 186 #define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20) 187 #define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21) 188 #define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22) 189 #define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23) 190 #define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24) 191 #define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25) 192 #define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26) 193 #define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27) 194 #define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28) 195 #define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29) 196 #define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30) 197 #define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31) 198 199 /* noc registers define */ 200 #define DEVICECONF 0x8 201 #define DEVICESIZE 0xc 202 #define DDRTIMINGA0 0x10 203 #define DDRTIMINGB0 0x14 204 #define DDRTIMINGC0 0x18 205 #define DEVTODEV0 0x1c 206 #define DDRMODE 0x110 207 #define DDR4TIMING 0x114 208 #define AGINGX0 0x1000 209 #define AGING0 0x1040 210 #define AGING1 0x1044 211 #define AGING2 0x1048 212 #define AGING3 0x104c 213 214 /* PMUGRF */ 215 #define PMUGRF_OS_REG0 (0x200) 216 #define PMUGRF_OS_REG(n) (PMUGRF_OS_REG0 + (n) * 4) 217 218 /* DDR GRF */ 219 #define DDR_GRF_CON(n) (0 + (n) * 4) 220 #define DDR_GRF_STATUS_BASE (0X100) 221 #define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) 222 #define DDR_GRF_LP_CON (0x20) 223 224 #define SPLIT_MODE_32_L16_VALID (0) 225 #define SPLIT_MODE_32_H16_VALID (1) 226 #define SPLIT_MODE_16_L8_VALID (2) 227 #define SPLIT_MODE_16_H8_VALID (3) 228 229 #define DDR_GRF_SPLIT_CON (0x8) 230 #define SPLIT_MODE_MASK (0x3) 231 #define SPLIT_MODE_OFFSET (9) 232 #define SPLIT_BYPASS_MASK (1) 233 #define SPLIT_BYPASS_OFFSET (8) 234 #define SPLIT_SIZE_MASK (0xff) 235 #define SPLIT_SIZE_OFFSET (0) 236 237 /* 238 * sys_reg bitfield struct 239 * [31] row_3_4_ch1 240 * [30] row_3_4_ch0 241 * [29:28] chinfo 242 * [27] rank_ch1 243 * [26:25] col_ch1 244 * [24] bk_ch1 245 * [23:22] cs0_row_ch1 246 * [21:20] cs1_row_ch1 247 * [19:18] bw_ch1 248 * [17:16] dbw_ch1; 249 * [15:13] ddrtype 250 * [12] channelnum 251 * [11] rank_ch0 252 * [10:9] col_ch0 253 * [8] bk_ch0 254 * [7:6] cs0_row_ch0 255 * [5:4] cs1_row_ch0 256 * [3:2] bw_ch0 257 * [1:0] dbw_ch0 258 */ 259 260 #define DDR_SYS_REG_VERSION (0x2) 261 #define SYS_REG_ENC_ROW_3_4(n) ((n) << 30) 262 #define SYS_REG_DEC_ROW_3_4(n) (((n) >> 30) & 0x1) 263 #define SYS_REG_ENC_CHINFO() (1 << 28) 264 #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) 265 #define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7) 266 #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) 267 #define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1)) 268 #define SYS_REG_ENC_RANK(n) (((n) - 1) << 11) 269 #define SYS_REG_DEC_RANK(n) (1 + (((n) >> 11) & 0x1)) 270 #define SYS_REG_ENC_COL(n) (((n) - 9) << 9) 271 #define SYS_REG_DEC_COL(n) (9 + (((n) >> 9) & 0x3)) 272 #define SYS_REG_ENC_BK(n) (((n) == 3 ? 0 : 1) << 8) 273 #define SYS_REG_DEC_BK(n) (3 - (((n) >> 8) & 0x1)) 274 #define SYS_REG_ENC_CS0_ROW(n) (((n) - 13) << 6) 275 #define SYS_REG_DEC_CS0_ROW(n) (13 + (((n) >> 6) & 0x3)) 276 #define SYS_REG_ENC_BW(n) ((2 >> (n)) << 2) 277 #define SYS_REG_DEC_BW(n) (2 >> (((n) >> 2) & 0x3)) 278 #define SYS_REG_ENC_DBW(n) ((2 >> (n)) << 0) 279 #define SYS_REG_DEC_DBW(n) (2 >> (((n) >> 0) & 0x3)) 280 /* sys reg 3 */ 281 #define SYS_REG_ENC_VERSION(n) ((n) << 28) 282 #define SYS_REG_DEC_VERSION(n) (((n) >> 28) & 0xf) 283 #define SYS_REG_ENC_CS0_ROW_(n, os_reg2, os_reg3) do { \ 284 (os_reg2) |= (((n) - 13) & 0x3) << 6;\ 285 (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << 5; \ 286 } while (0) 287 288 #define SYS_REG_DEC_CS0_ROW_(os_reg2, os_reg3) \ 289 ((((((os_reg2) >> 6 & 0x3) | \ 290 ((((os_reg3) >> 5) & 0x1) << 2)) + 1) & 0x7) + 12) 291 292 #define SYS_REG_ENC_CS1_ROW_(n, os_reg2, os_reg3) do { \ 293 (os_reg2) &= (~(0x3 << 4));\ 294 (os_reg3) &= (~(0x1 << 4));\ 295 (os_reg2) |= (((n) - 13) & 0x3) << 4;\ 296 (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << 4; \ 297 } while (0) 298 299 #define SYS_REG_DEC_CS1_ROW_(os_reg2, os_reg3) \ 300 ((((((os_reg2) >> 4 & 0x3) | \ 301 ((((os_reg3) >> 4) & 0x1) << 2)) + 1) & 0x7) + 12) 302 303 #define SYS_REG_ENC_CS1_COL(n) (((n) - 9) << 0) 304 #define SYS_REG_DEC_CS1_COL(n) (9 + (((n) >> 0) & 0x3)) 305 306 /* CRU define */ 307 /* CRU_PLL_CON0 */ 308 #define PB(n) ((0x1 << (15 + 16)) | ((n) << 15)) 309 #define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12)) 310 #define FBDIV(n) ((0xFFF << 16) | (n)) 311 312 /* CRU_PLL_CON1 */ 313 #define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15)) 314 #define RST(n) ((0x1 << (14 + 16)) | ((n) << 14)) 315 #define PD(n) ((0x1 << (13 + 16)) | ((n) << 13)) 316 #define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12)) 317 #define LOCK(n) (((n) >> 10) & 0x1) 318 #define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6)) 319 #define REFDIV(n) ((0x3F << 16) | (n)) 320 321 /* CRU_MODE */ 322 #define CLOCK_FROM_XIN_OSC (0) 323 #define CLOCK_FROM_PLL (1) 324 #define CLOCK_FROM_RTC_32K (2) 325 #define DPLL_MODE(n) ((0x3 << (4 + 16)) | ((n) << 4)) 326 327 /* CRU_SOFTRESET_CON1 */ 328 #define upctl2_psrstn_req(n) (((0x1 << 6) << 16) | ((n) << 6)) 329 #define upctl2_asrstn_req(n) (((0x1 << 5) << 16) | ((n) << 5)) 330 #define upctl2_srstn_req(n) (((0x1 << 4) << 16) | ((n) << 4)) 331 332 /* CRU_SOFTRESET_CON2 */ 333 #define ddrphy_psrstn_req(n) (((0x1 << 2) << 16) | ((n) << 2)) 334 #define ddrphy_srstn_req(n) (((0x1 << 0) << 16) | ((n) << 0)) 335 336 /* CRU register */ 337 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) 338 #define CRU_MODE (0xa0) 339 #define CRU_GLB_CNT_TH (0xb0) 340 #define CRU_CLKSEL_CON_BASE 0x100 341 #define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON_BASE + ((i) * 4)) 342 #define CRU_CLKGATE_CON_BASE 0x200 343 #define CRU_CLKGATE_CON(i) (CRU_CLKGATE_CON_BASE + ((i) * 4)) 344 #define CRU_CLKSFTRST_CON_BASE 0x300 345 #define CRU_CLKSFTRST_CON(i) (CRU_CLKSFTRST_CON_BASE + ((i) * 4)) 346 347 u8 ddr_cfg_2_rbc[] = { 348 /* 349 * [6:4] max row: 13+n 350 * [3] bank(0:4bank,1:8bank) 351 * [2:0] col(10+n) 352 */ 353 ((5 << 4) | (1 << 3) | 0), /* 0 */ 354 ((5 << 4) | (1 << 3) | 1), /* 1 */ 355 ((4 << 4) | (1 << 3) | 2), /* 2 */ 356 ((3 << 4) | (1 << 3) | 3), /* 3 */ 357 ((2 << 4) | (1 << 3) | 4), /* 4 */ 358 ((5 << 4) | (0 << 3) | 2), /* 5 */ 359 ((4 << 4) | (1 << 3) | 2), /* 6 */ 360 /*((0<<3)|3),*/ /* 12 for ddr4 */ 361 /*((1<<3)|1),*/ /* 13 B,C exchange for rkvdec */ 362 }; 363 364 /* 365 * for ddr4 if ddrconfig=7, upctl should set 7 and noc should 366 * set to 1 for more efficient. 367 * noc ddrconf, upctl addrmap 368 * 1 7 369 * 2 8 370 * 3 9 371 * 12 10 372 * 5 11 373 */ 374 u8 d4_rbc_2_d3_rbc[] = { 375 1, /* 7 */ 376 2, /* 8 */ 377 3, /* 9 */ 378 12, /* 10 */ 379 5, /* 11 */ 380 }; 381 382 /* 383 * row higher than cs should be disabled by set to 0xf 384 * rank addrmap calculate by real cap. 385 */ 386 u32 addrmap[][8] = { 387 /* map0 map1, map2, map3, map4, map5 388 * map6, map7, map8 389 * ------------------------------------------------------- 390 * bk2-0 col 5-2 col 9-6 col 11-10 row 11-0 391 * row 15-12 row 17-16 bg1,0 392 * ------------------------------------------------------- 393 * 4,3,2 5-2 9-6 6 394 * 3,2 395 */ 396 {0x00060606, 0x00000000, 0x1f1f0000, 0x00001f1f, 0x05050505, 397 0x05050505, 0x00000505, 0x3f3f}, /* 0 */ 398 {0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606, 399 0x06060606, 0x06060606, 0x3f3f}, /* 1 */ 400 {0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, 401 0x07070707, 0x00000f07, 0x3f3f}, /* 2 */ 402 {0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808, 403 0x08080808, 0x00000f0f, 0x3f3f}, /* 3 */ 404 {0x000a0a0a, 0x00000000, 0x00000000, 0x00000000, 0x09090909, 405 0x0f090909, 0x00000f0f, 0x3f3f}, /* 4 */ 406 {0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606, 407 0x06060606, 0x00000606, 0x3f3f}, /* 5 */ 408 {0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, 409 0x07070707, 0x00000f0f, 0x3f3f}, /* 6 */ 410 {0x003f0808, 0x00000006, 0x1f1f0000, 0x00001f1f, 0x06060606, 411 0x06060606, 0x00000606, 0x0600}, /* 7 */ 412 {0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, 413 0x07070707, 0x00000f07, 0x0700}, /* 8 */ 414 {0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, 415 0x08080808, 0x00000f0f, 0x0801}, /* 9 */ 416 {0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, 417 0x07070707, 0x00000f07, 0x3f01}, /* 10 */ 418 {0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x06060606, 419 0x06060606, 0x00000606, 0x3f00}, /* 11 */ 420 /* when ddr4 12 map to 10, when ddr3 12 unused */ 421 {0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, 422 0x07070707, 0x00000f07, 0x3f01}, /* 10 */ 423 {0x00070706, 0x00000000, 0x1f010000, 0x00001f1f, 0x06060606, 424 0x06060606, 0x00000606, 0x3f3f}, /* 13 */ 425 }; 426 427 union noc_ddrtiminga0 { 428 u32 d32; 429 struct { 430 unsigned acttoact : 6; 431 unsigned reserved0 : 2; 432 unsigned rdtomiss : 6; 433 unsigned reserved1 : 2; 434 unsigned wrtomiss : 6; 435 unsigned reserved2 : 2; 436 unsigned readlatency : 8; 437 } b; 438 }; 439 440 union noc_ddrtimingb0 { 441 u32 d32; 442 struct { 443 unsigned rdtowr : 5; 444 unsigned reserved0 : 3; 445 unsigned wrtord : 5; 446 unsigned reserved1 : 3; 447 unsigned rrd : 4; 448 unsigned reserved2 : 4; 449 unsigned faw : 6; 450 unsigned reserved3 : 2; 451 } b; 452 }; 453 454 union noc_ddrtimingc0 { 455 u32 d32; 456 struct { 457 unsigned burstpenalty : 4; 458 unsigned reserved0 : 4; 459 unsigned wrtomwr : 6; 460 unsigned reserved1 : 18; 461 } b; 462 }; 463 464 union noc_devtodev0 { 465 u32 d32; 466 struct { 467 unsigned busrdtord : 3; 468 unsigned reserved0 : 1; 469 unsigned busrdtowr : 3; 470 unsigned reserved1 : 1; 471 unsigned buswrtord : 3; 472 unsigned reserved2 : 1; 473 unsigned buswrtowr : 3; 474 unsigned reserved3 : 17; 475 } b; 476 }; 477 478 union noc_ddrmode { 479 u32 d32; 480 struct { 481 unsigned autoprecharge : 1; 482 unsigned bypassfiltering : 1; 483 unsigned fawbank : 1; 484 unsigned burstsize : 2; 485 unsigned mwrsize : 2; 486 unsigned reserved2 : 1; 487 unsigned forceorder : 8; 488 unsigned forceorderstate : 8; 489 unsigned reserved3 : 8; 490 } b; 491 }; 492 493 union noc_ddr4timing { 494 u32 d32; 495 struct { 496 unsigned ccdl : 3; 497 unsigned wrtordl : 5; 498 unsigned rrdl : 4; 499 unsigned reserved1 : 20; 500 } b; 501 }; 502 503 struct px30_msch_timings { 504 union noc_ddrtiminga0 ddrtiminga0; 505 union noc_ddrtimingb0 ddrtimingb0; 506 union noc_ddrtimingc0 ddrtimingc0; 507 union noc_devtodev0 devtodev0; 508 union noc_ddrmode ddrmode; 509 union noc_ddr4timing ddr4timing; 510 u32 agingx0; 511 }; 512 513 struct px30_msch_regs { 514 u32 coreid; 515 u32 revisionid; 516 u32 deviceconf; 517 u32 devicesize; 518 u32 ddrtiminga0; 519 u32 ddrtimingb0; 520 u32 ddrtimingc0; 521 u32 devtodev0; 522 u32 reserved1[(0x110 - 0x20) / 4]; 523 u32 ddrmode; 524 u32 ddr4timing; 525 u32 reserved2[(0x1000 - 0x118) / 4]; 526 u32 agingx0; 527 u32 reserved3[(0x1040 - 0x1004) / 4]; 528 u32 aging0; 529 u32 aging1; 530 u32 aging2; 531 u32 aging3; 532 }; 533 534 struct px30_ddr_grf_regs { 535 u32 ddr_grf_con[4]; 536 u32 reserved1[(0x20 - 0x10) / 4]; 537 u32 ddr_grf_lp_con; 538 u32 reserved2[(0x100 - 0x24) / 4]; 539 u32 ddr_grf_status[11]; 540 }; 541 542 struct px30_ddr_pctl_regs { 543 u32 pctl[30][2]; 544 }; 545 546 struct px30_ddr_phy_regs { 547 u32 phy[5][2]; 548 }; 549 550 struct px30_ddr_skew { 551 u32 a0_a1_skew[15]; 552 u32 cs0_dm0_skew[11]; 553 u32 cs0_dm1_skew[11]; 554 u32 cs0_dm2_skew[11]; 555 u32 cs0_dm3_skew[11]; 556 u32 cs1_dm0_skew[11]; 557 u32 cs1_dm1_skew[11]; 558 u32 cs1_dm2_skew[11]; 559 u32 cs1_dm3_skew[11]; 560 }; 561 562 struct px30_sdram_channel { 563 unsigned char rank; 564 unsigned char col; 565 /* 3:8bank, 2:4bank */ 566 unsigned char bk; 567 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ 568 unsigned char bw; 569 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ 570 unsigned char dbw; 571 unsigned char row_3_4; 572 unsigned char cs0_row; 573 unsigned char cs1_row; 574 unsigned char cs0_high16bit_row; 575 unsigned char cs1_high16bit_row; 576 unsigned int ddrconfig; 577 struct px30_msch_timings noc_timings; 578 }; 579 580 struct px30_sdram_params { 581 struct px30_sdram_channel ch; 582 unsigned int ddr_freq; 583 unsigned int dramtype; 584 unsigned int odt; 585 struct px30_ddr_pctl_regs pctl_regs; 586 struct px30_ddr_phy_regs phy_regs; 587 struct px30_ddr_skew *skew; 588 }; 589 590 #define PHY_REG(base, n) ((base) + 4 * (n)) 591 592 #endif 593