xref: /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/rockchip_smccc.h (revision 16a92a426ee3d8bcd4aba3ee039c6e94031d7fbd)
1 /*
2  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 
7 #ifndef __ROCKCHIP_SMCCC_H__
8 #define __ROCKCHIP_SMCCC_H__
9 
10 /* Rockchip platform SiP call ID */
11 #define SIP_ATF_VERSION			0x82000001
12 #define SIP_ACCESS_REG			0x82000002
13 #define SIP_SUSPEND_MODE		0x82000003
14 #define SIP_PENDING_CPUS		0x82000004
15 #define SIP_UARTDBG_CFG			0x82000005
16 #define SIP_UARTDBG_CFG64		0xc2000005
17 #define SIP_MCU_EL3FIQ_CFG		0x82000006
18 #define SIP_ACCESS_CHIP_STATE64		0xc2000006
19 #define SIP_SECURE_MEM_CONFIG		0x82000007
20 #define SIP_ACCESS_CHIP_EXTRA_STATE64	0xc2000007
21 #define SIP_DRAM_CONFIG			0x82000008
22 #define SIP_SHARE_MEM			0x82000009
23 #define SIP_SIP_VERSION			0x8200000a
24 #define SIP_REMOTECTL_CFG		0x8200000b
25 #define PSCI_SIP_VPU_RESET		0x8200000c
26 
27 #define ROCKCHIP_SIP_CONFIG_DRAM_INIT		0x00
28 #define ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE	0x01
29 #define ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE	0x02
30 #define ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR	0x03
31 #define ROCKCHIP_SIP_CONFIG_DRAM_GET_BW		0x04
32 #define ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE	0x05
33 #define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ	0x06
34 #define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM	0x07
35 #define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION	0x08
36 
37 /* Rockchip Sip version */
38 #define SIP_IMPLEMENT_V1                (1)
39 #define SIP_IMPLEMENT_V2                (2)
40 
41 /* Error return code */
42 #define IS_SIP_ERROR(x)			(!!(x))
43 
44 #define SIP_RET_SUCCESS			0
45 #define SIP_RET_SMC_UNKNOWN		-1
46 #define SIP_RET_NOT_SUPPORTED		-2
47 #define SIP_RET_INVALID_PARAMS		-3
48 #define SIP_RET_INVALID_ADDRESS		-4
49 #define SIP_RET_DENIED			-5
50 
51 /* SIP_ACCESS_REG: read or write */
52 #define SECURE_REG_RD			0x0
53 #define SECURE_REG_WR			0x1
54 
55 /* Share mem page types */
56 typedef enum {
57 	SHARE_PAGE_TYPE_INVALID = 0,
58 	SHARE_PAGE_TYPE_UARTDBG,
59 	SHARE_PAGE_TYPE_DDR,
60 	SHARE_PAGE_TYPE_MAX,
61 } share_page_type_t;
62 
63 /* Stand PSCI system suspend */
64 int psci_system_suspend(unsigned long unused);
65 
66 /* Rockchip SMC Calls */
67 int sip_smc_set_suspend_mode(unsigned long ctrl,
68 			     unsigned long config1,
69 			     unsigned long config2);
70 
71 struct arm_smccc_res sip_smc_dram(unsigned long arg0,
72 				  unsigned long arg1,
73 				  unsigned long arg2);
74 
75 struct arm_smccc_res sip_smc_request_share_mem(unsigned long page_num,
76 					       share_page_type_t page_type);
77 
78 int sip_smc_set_sip_version(unsigned long version);
79 struct arm_smccc_res sip_smc_get_sip_version(void);
80 int psci_cpu_on(unsigned long cpuid, unsigned long entry_point);
81 
82 #endif
83