1*95b95808SZhihuan He /* 2*95b95808SZhihuan He * Copyright (C) 2018 Rockchip Electronics Co., Ltd 3*95b95808SZhihuan He * Author: Zhihuan He <huan.he@rock-chips.com> 4*95b95808SZhihuan He * SPDX-License-Identifier: GPL-2.0 5*95b95808SZhihuan He */ 6*95b95808SZhihuan He 7*95b95808SZhihuan He #ifndef _ASM_ARCH_PMU_RV1108_H 8*95b95808SZhihuan He #define _ASM_ARCH_PMU_RV1108_H 9*95b95808SZhihuan He 10*95b95808SZhihuan He struct rv1108_pmu { 11*95b95808SZhihuan He u32 wakeup_cfg[3]; 12*95b95808SZhihuan He u32 reserved0[2]; 13*95b95808SZhihuan He u32 pwrmode_core_con; 14*95b95808SZhihuan He u32 pwrmode_common_con; 15*95b95808SZhihuan He u32 sft_con; 16*95b95808SZhihuan He u32 reserved1[7]; 17*95b95808SZhihuan He u32 bus_idle_req; 18*95b95808SZhihuan He u32 bus_idle_st; 19*95b95808SZhihuan He u32 reserved2; 20*95b95808SZhihuan He u32 osc_cnt; 21*95b95808SZhihuan He u32 plllock_cnt; 22*95b95808SZhihuan He u32 reserved3; 23*95b95808SZhihuan He u32 stable_cnt; 24*95b95808SZhihuan He u32 reserved4; 25*95b95808SZhihuan He u32 wakeup_rst_clr_cnt; 26*95b95808SZhihuan He u32 ddr_sref_st; 27*95b95808SZhihuan He u32 sys_reg[4]; 28*95b95808SZhihuan He u32 timeout_cnt; 29*95b95808SZhihuan He }; 30*95b95808SZhihuan He 31*95b95808SZhihuan He check_member(rv1108_pmu, timeout_cnt, 0x0074); 32*95b95808SZhihuan He 33*95b95808SZhihuan He enum { /* PMU_SFT_CON */ 34*95b95808SZhihuan He DDR_IO_RET_SHIFT = 11, 35*95b95808SZhihuan He DDR_IO_RET_EN = 1 << DDR_IO_RET_SHIFT, 36*95b95808SZhihuan He }; 37*95b95808SZhihuan He 38*95b95808SZhihuan He #endif 39*95b95808SZhihuan He 40