1*8b36ec9fSYouMin Chen /* SPDX-License-Identifier: GPL-2.0+ */ 2*8b36ec9fSYouMin Chen /* 3*8b36ec9fSYouMin Chen * (C) Copyright 2018 Rockchip Electronics Co., Ltd. 4*8b36ec9fSYouMin Chen * 5*8b36ec9fSYouMin Chen */ 6*8b36ec9fSYouMin Chen 7*8b36ec9fSYouMin Chen #ifndef __SOC_ROCKCHIP_RK3399_PMU_H__ 8*8b36ec9fSYouMin Chen #define __SOC_ROCKCHIP_RK3399_PMU_H__ 9*8b36ec9fSYouMin Chen 10*8b36ec9fSYouMin Chen struct rk3399_pmu_regs { 11*8b36ec9fSYouMin Chen u32 pmu_wakeup_cfg[5]; 12*8b36ec9fSYouMin Chen u32 pmu_pwrdn_con; 13*8b36ec9fSYouMin Chen u32 pmu_pwrdn_st; 14*8b36ec9fSYouMin Chen u32 pmu_pll_con; 15*8b36ec9fSYouMin Chen u32 pmu_pwrmode_con; 16*8b36ec9fSYouMin Chen u32 pmu_sft_con; 17*8b36ec9fSYouMin Chen u32 pmu_int_con; 18*8b36ec9fSYouMin Chen u32 pmu_int_st; 19*8b36ec9fSYouMin Chen u32 pmu_gpio0_pos_int_con; 20*8b36ec9fSYouMin Chen u32 pmu_gpio0_net_int_con; 21*8b36ec9fSYouMin Chen u32 pmu_gpio1_pos_int_con; 22*8b36ec9fSYouMin Chen u32 pmu_gpio1_net_int_con; 23*8b36ec9fSYouMin Chen u32 pmu_gpio0_pos_int_st; 24*8b36ec9fSYouMin Chen u32 pmu_gpio0_net_int_st; 25*8b36ec9fSYouMin Chen u32 pmu_gpio1_pos_int_st; 26*8b36ec9fSYouMin Chen u32 pmu_gpio1_net_int_st; 27*8b36ec9fSYouMin Chen u32 pmu_pwrdn_inten; 28*8b36ec9fSYouMin Chen u32 pmu_pwrdn_status; 29*8b36ec9fSYouMin Chen u32 pmu_wakeup_status; 30*8b36ec9fSYouMin Chen u32 pmu_bus_clr; 31*8b36ec9fSYouMin Chen u32 pmu_bus_idle_req; 32*8b36ec9fSYouMin Chen u32 pmu_bus_idle_st; 33*8b36ec9fSYouMin Chen u32 pmu_bus_idle_ack; 34*8b36ec9fSYouMin Chen u32 pmu_cci500_con; 35*8b36ec9fSYouMin Chen u32 pmu_adb400_con; 36*8b36ec9fSYouMin Chen u32 pmu_adb400_st; 37*8b36ec9fSYouMin Chen u32 pmu_power_st; 38*8b36ec9fSYouMin Chen u32 pmu_core_pwr_st; 39*8b36ec9fSYouMin Chen u32 pmu_osc_cnt; 40*8b36ec9fSYouMin Chen u32 pmu_plllock_cnt; 41*8b36ec9fSYouMin Chen u32 pmu_pllrst_cnt; 42*8b36ec9fSYouMin Chen u32 pmu_stable_cnt; 43*8b36ec9fSYouMin Chen u32 pmu_ddrio_pwron_cnt; 44*8b36ec9fSYouMin Chen u32 pmu_wakeup_rst_clr_cnt; 45*8b36ec9fSYouMin Chen u32 pmu_ddr_sref_st; 46*8b36ec9fSYouMin Chen u32 pmu_scu_l_pwrdn_cnt; 47*8b36ec9fSYouMin Chen u32 pmu_scu_l_pwrup_cnt; 48*8b36ec9fSYouMin Chen u32 pmu_scu_b_pwrdn_cnt; 49*8b36ec9fSYouMin Chen u32 pmu_scu_b_pwrup_cnt; 50*8b36ec9fSYouMin Chen u32 pmu_gpu_pwrdn_cnt; 51*8b36ec9fSYouMin Chen u32 pmu_gpu_pwrup_cnt; 52*8b36ec9fSYouMin Chen u32 pmu_center_pwrdn_cnt; 53*8b36ec9fSYouMin Chen u32 pmu_center_pwrup_cnt; 54*8b36ec9fSYouMin Chen u32 pmu_timeout_cnt; 55*8b36ec9fSYouMin Chen u32 pmu_cpu0apm_con; 56*8b36ec9fSYouMin Chen u32 pmu_cpu1apm_con; 57*8b36ec9fSYouMin Chen u32 pmu_cpu2apm_con; 58*8b36ec9fSYouMin Chen u32 pmu_cpu3apm_con; 59*8b36ec9fSYouMin Chen u32 pmu_cpu0bpm_con; 60*8b36ec9fSYouMin Chen u32 pmu_cpu1bpm_con; 61*8b36ec9fSYouMin Chen u32 pmu_noc_auto_ena; 62*8b36ec9fSYouMin Chen u32 pmu_pwrdn_con1; 63*8b36ec9fSYouMin Chen u32 reserved0[0x4]; 64*8b36ec9fSYouMin Chen u32 pmu_sys_reg_reg0; 65*8b36ec9fSYouMin Chen u32 pmu_sys_reg_reg1; 66*8b36ec9fSYouMin Chen u32 pmu_sys_reg_reg2; 67*8b36ec9fSYouMin Chen u32 pmu_sys_reg_reg3; 68*8b36ec9fSYouMin Chen }; 69*8b36ec9fSYouMin Chen 70*8b36ec9fSYouMin Chen check_member(rk3399_pmu_regs, pmu_sys_reg_reg3, 0xfc); 71*8b36ec9fSYouMin Chen 72*8b36ec9fSYouMin Chen #endif /* __SOC_ROCKCHIP_RK3399_PMU_H__ */ 73