1 /* 2 * (C) Copyright 2021 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_IOC_RK3576_H 7 #define _ASM_ARCH_IOC_RK3576_H 8 9 #include <common.h> 10 11 /* pmu0_ioc register structure define */ 12 struct rk3576_pmu0_ioc_reg { 13 uint32_t gpio0a_iomux_sel_l; /* address offset: 0x0000 */ 14 uint32_t gpio0a_iomux_sel_h; /* address offset: 0x0004 */ 15 uint32_t gpio0b_iomux_sel_l; /* address offset: 0x0008 */ 16 uint32_t reserved000c; /* address offset: 0x000c */ 17 uint32_t gpio0a_ds_l; /* address offset: 0x0010 */ 18 uint32_t gpio0a_ds_h; /* address offset: 0x0014 */ 19 uint32_t gpio0b_ds_l; /* address offset: 0x0018 */ 20 uint32_t reserved001c; /* address offset: 0x001c */ 21 uint32_t gpio0a_pull; /* address offset: 0x0020 */ 22 uint32_t gpio0b_pull_l; /* address offset: 0x0024 */ 23 uint32_t gpio0a_ie; /* address offset: 0x0028 */ 24 uint32_t gpio0b_ie_l; /* address offset: 0x002c */ 25 uint32_t gpio0a_smt; /* address offset: 0x0030 */ 26 uint32_t gpio0b_smt_l; /* address offset: 0x0034 */ 27 uint32_t gpio0a_pdis; /* address offset: 0x0038 */ 28 uint32_t gpio0b_pdis_l; /* address offset: 0x003c */ 29 uint32_t osc_con; /* address offset: 0x0040 */ 30 }; 31 32 check_member(rk3576_pmu0_ioc_reg, osc_con, 0x0040); 33 34 /* pmu1_ioc register structure define */ 35 struct rk3576_pmu1_ioc_reg { 36 uint32_t gpio0b_iomux_sel_h; /* address offset: 0x0000 */ 37 uint32_t gpio0c_iomux_sel_l; /* address offset: 0x0004 */ 38 uint32_t gpio0c_iomux_sel_h; /* address offset: 0x0008 */ 39 uint32_t gpio0d_iomux_sel_l; /* address offset: 0x000c */ 40 uint32_t gpio0d_iomux_sel_h; /* address offset: 0x0010 */ 41 uint32_t gpio0b_ds_h; /* address offset: 0x0014 */ 42 uint32_t gpio0c_ds_l; /* address offset: 0x0018 */ 43 uint32_t gpio0c_ds_h; /* address offset: 0x001c */ 44 uint32_t gpio0d_ds_l; /* address offset: 0x0020 */ 45 uint32_t gpio0d_ds_h; /* address offset: 0x0024 */ 46 uint32_t gpio0b_pull_h; /* address offset: 0x0028 */ 47 uint32_t gpio0c_pull; /* address offset: 0x002c */ 48 uint32_t gpio0d_pull; /* address offset: 0x0030 */ 49 uint32_t gpio0b_ie_h; /* address offset: 0x0034 */ 50 uint32_t gpio0c_ie; /* address offset: 0x0038 */ 51 uint32_t gpio0d_ie; /* address offset: 0x003c */ 52 uint32_t gpio0b_smt_h; /* address offset: 0x0040 */ 53 uint32_t gpio0c_smt; /* address offset: 0x0044 */ 54 uint32_t gpio0d_smt; /* address offset: 0x0048 */ 55 uint32_t gpio0b_pdis_h; /* address offset: 0x004c */ 56 uint32_t gpio0c_pdis; /* address offset: 0x0050 */ 57 uint32_t gpio0d_pdis; /* address offset: 0x0054 */ 58 }; 59 60 check_member(rk3576_pmu1_ioc_reg, gpio0d_pdis, 0x0054); 61 62 /* top_ioc register structure define */ 63 struct rk3576_top_ioc_reg { 64 uint32_t reserved0000[2]; /* address offset: 0x0000 */ 65 uint32_t gpio0b_iomux_sel_l; /* address offset: 0x0008 */ 66 uint32_t gpio0b_iomux_sel_h; /* address offset: 0x000c */ 67 uint32_t gpio0c_iomux_sel_l; /* address offset: 0x0010 */ 68 uint32_t gpio0c_iomux_sel_h; /* address offset: 0x0014 */ 69 uint32_t gpio0d_iomux_sel_l; /* address offset: 0x0018 */ 70 uint32_t gpio0d_iomux_sel_h; /* address offset: 0x001c */ 71 uint32_t gpio1a_iomux_sel_l; /* address offset: 0x0020 */ 72 uint32_t gpio1a_iomux_sel_h; /* address offset: 0x0024 */ 73 uint32_t gpio1b_iomux_sel_l; /* address offset: 0x0028 */ 74 uint32_t gpio1b_iomux_sel_h; /* address offset: 0x002c */ 75 uint32_t gpio1c_iomux_sel_l; /* address offset: 0x0030 */ 76 uint32_t gpio1c_iomux_sel_h; /* address offset: 0x0034 */ 77 uint32_t gpio1d_iomux_sel_l; /* address offset: 0x0038 */ 78 uint32_t gpio1d_iomux_sel_h; /* address offset: 0x003c */ 79 uint32_t gpio2a_iomux_sel_l; /* address offset: 0x0040 */ 80 uint32_t gpio2a_iomux_sel_h; /* address offset: 0x0044 */ 81 uint32_t gpio2b_iomux_sel_l; /* address offset: 0x0048 */ 82 uint32_t gpio2b_iomux_sel_h; /* address offset: 0x004c */ 83 uint32_t gpio2c_iomux_sel_l; /* address offset: 0x0050 */ 84 uint32_t gpio2c_iomux_sel_h; /* address offset: 0x0054 */ 85 uint32_t gpio2d_iomux_sel_l; /* address offset: 0x0058 */ 86 uint32_t gpio2d_iomux_sel_h; /* address offset: 0x005c */ 87 uint32_t gpio3a_iomux_sel_l; /* address offset: 0x0060 */ 88 uint32_t gpio3a_iomux_sel_h; /* address offset: 0x0064 */ 89 uint32_t gpio3b_iomux_sel_l; /* address offset: 0x0068 */ 90 uint32_t gpio3b_iomux_sel_h; /* address offset: 0x006c */ 91 uint32_t gpio3c_iomux_sel_l; /* address offset: 0x0070 */ 92 uint32_t gpio3c_iomux_sel_h; /* address offset: 0x0074 */ 93 uint32_t gpio3d_iomux_sel_l; /* address offset: 0x0078 */ 94 uint32_t gpio3d_iomux_sel_h; /* address offset: 0x007c */ 95 uint32_t gpio4a_iomux_sel_l; /* address offset: 0x0080 */ 96 uint32_t gpio4a_iomux_sel_h; /* address offset: 0x0084 */ 97 uint32_t gpio4b_iomux_sel_l; /* address offset: 0x0088 */ 98 uint32_t gpio4b_iomux_sel_h; /* address offset: 0x008c */ 99 uint32_t reserved0090[24]; /* address offset: 0x0090 */ 100 uint32_t ioc_misc_con; /* address offset: 0x00f0 */ 101 uint32_t sdmmc_detn_flt; /* address offset: 0x00f4 */ 102 }; 103 104 check_member(rk3576_top_ioc_reg, sdmmc_detn_flt, 0x00f4); 105 106 #endif /* _ASM_ARCH_IOC_RK3576_H */