134374699SSimon Glass /* 234374699SSimon Glass * (C) Copyright 2012 SAMSUNG Electronics 334374699SSimon Glass * Jaehoon Chung <jh80.chung@samsung.com> 434374699SSimon Glass * 534374699SSimon Glass * SPDX-License-Identifier: GPL-2.0+ 634374699SSimon Glass */ 734374699SSimon Glass 834374699SSimon Glass #ifndef __ASM_ARCH_I2C_H 934374699SSimon Glass #define __ASM_ARCH_I2C_H 1034374699SSimon Glass 1134374699SSimon Glass struct i2c_regs { 1234374699SSimon Glass u32 con; 1334374699SSimon Glass u32 clkdiv; 1434374699SSimon Glass u32 mrxaddr; 1534374699SSimon Glass u32 mrxraddr; 1634374699SSimon Glass u32 mtxcnt; 1734374699SSimon Glass u32 mrxcnt; 1834374699SSimon Glass u32 ien; 1934374699SSimon Glass u32 ipd; 2034374699SSimon Glass u32 fcnt; 2134374699SSimon Glass u32 reserved0[0x37]; 2234374699SSimon Glass u32 txdata[8]; 2334374699SSimon Glass u32 reserved1[0x38]; 2434374699SSimon Glass u32 rxdata[8]; 2534374699SSimon Glass }; 2634374699SSimon Glass 2734374699SSimon Glass /* Control register */ 2834374699SSimon Glass #define I2C_CON_EN (1 << 0) 2934374699SSimon Glass #define I2C_CON_MOD(mod) ((mod) << 1) 3034374699SSimon Glass #define I2C_MODE_TX 0x00 3134374699SSimon Glass #define I2C_MODE_TRX 0x01 3234374699SSimon Glass #define I2C_MODE_RX 0x02 3334374699SSimon Glass #define I2C_MODE_RRX 0x03 3434374699SSimon Glass #define I2C_CON_MASK (3 << 1) 3534374699SSimon Glass 3634374699SSimon Glass #define I2C_CON_START (1 << 3) 3734374699SSimon Glass #define I2C_CON_STOP (1 << 4) 3834374699SSimon Glass #define I2C_CON_LASTACK (1 << 5) 3934374699SSimon Glass #define I2C_CON_ACTACK (1 << 6) 40*3d5347f8SDavid Wu #define I2C_CON_TUNING_MASK (0xff << 8) 41*3d5347f8SDavid Wu #define I2C_CON_SDA_CFG(cfg) ((cfg) << 8) 42*3d5347f8SDavid Wu #define I2C_CON_STA_CFG(cfg) ((cfg) << 12) 43*3d5347f8SDavid Wu #define I2C_CON_STO_CFG(cfg) ((cfg) << 14) 44*3d5347f8SDavid Wu #define I2C_CON_VERSION GENMASK_ULL(24, 16) 45*3d5347f8SDavid Wu #define I2C_CON_VERSION_SHIFT 16 4634374699SSimon Glass 4734374699SSimon Glass /* Clock dividor register */ 48*3d5347f8SDavid Wu #define I2C_CLK_DIV_HIGH_SHIFT 16 4934374699SSimon Glass #define I2C_CLKDIV_VAL(divl, divh) \ 5034374699SSimon Glass (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000)) 5134374699SSimon Glass 5234374699SSimon Glass /* the slave address accessed for master rx mode */ 5334374699SSimon Glass #define I2C_MRXADDR_SET(vld, addr) (((vld) << 24) | (addr)) 5434374699SSimon Glass 5534374699SSimon Glass /* the slave register address accessed for master rx mode */ 5634374699SSimon Glass #define I2C_MRXRADDR_SET(vld, raddr) (((vld) << 24) | (raddr)) 5734374699SSimon Glass 5834374699SSimon Glass /* interrupt enable register */ 5934374699SSimon Glass #define I2C_BTFIEN (1 << 0) 6034374699SSimon Glass #define I2C_BRFIEN (1 << 1) 6134374699SSimon Glass #define I2C_MBTFIEN (1 << 2) 6234374699SSimon Glass #define I2C_MBRFIEN (1 << 3) 6334374699SSimon Glass #define I2C_STARTIEN (1 << 4) 6434374699SSimon Glass #define I2C_STOPIEN (1 << 5) 6534374699SSimon Glass #define I2C_NAKRCVIEN (1 << 6) 6634374699SSimon Glass 6734374699SSimon Glass /* interrupt pending register */ 6834374699SSimon Glass #define I2C_BTFIPD (1 << 0) 6934374699SSimon Glass #define I2C_BRFIPD (1 << 1) 7034374699SSimon Glass #define I2C_MBTFIPD (1 << 2) 7134374699SSimon Glass #define I2C_MBRFIPD (1 << 3) 7234374699SSimon Glass #define I2C_STARTIPD (1 << 4) 7334374699SSimon Glass #define I2C_STOPIPD (1 << 5) 7434374699SSimon Glass #define I2C_NAKRCVIPD (1 << 6) 7534374699SSimon Glass #define I2C_IPD_ALL_CLEAN 0x7f 7634374699SSimon Glass 7734374699SSimon Glass #endif 78