1 /* 2 * Copyright (C) 2018 Rockchip Electronics Co., Ltd 3 * Author: Zhihuan He <huan.he@rock-chips.com> 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARCH_GRF_RV1108_H 8 #define _ASM_ARCH_GRF_RV1108_H 9 10 #include <common.h> 11 12 struct rv1108_grf { 13 u32 reserved[4]; 14 u32 gpio1a_iomux; 15 u32 gpio1b_iomux; 16 u32 gpio1c_iomux; 17 u32 gpio1d_iomux; 18 u32 gpio2a_iomux; 19 u32 gpio2b_iomux; 20 u32 gpio2c_iomux; 21 u32 gpio2d_iomux; 22 u32 gpio3a_iomux; 23 u32 gpio3b_iomux; 24 u32 gpio3c_iomux; 25 u32 gpio3d_iomux; 26 u32 reserved1[52]; 27 u32 gpio1a_pull; 28 u32 gpio1b_pull; 29 u32 gpio1c_pull; 30 u32 gpio1d_pull; 31 u32 gpio2a_pull; 32 u32 gpio2b_pull; 33 u32 gpio2c_pull; 34 u32 gpio2d_pull; 35 u32 gpio3a_pull; 36 u32 gpio3b_pull; 37 u32 gpio3c_pull; 38 u32 gpio3d_pull; 39 u32 reserved2[52]; 40 u32 gpio1a_drv; 41 u32 gpio1b_drv; 42 u32 gpio1c_drv; 43 u32 gpio1d_drv; 44 u32 gpio2a_drv; 45 u32 gpio2b_drv; 46 u32 gpio2c_drv; 47 u32 gpio2d_drv; 48 u32 gpio3a_drv; 49 u32 gpio3b_drv; 50 u32 gpio3c_drv; 51 u32 gpio3d_drv; 52 u32 reserved3[50]; 53 u32 gpio1l_sr; 54 u32 gpio1h_sr; 55 u32 gpio2l_sr; 56 u32 gpio2h_sr; 57 u32 gpio3l_sr; 58 u32 gpio3h_sr; 59 u32 reserved4[26]; 60 u32 gpio1l_smt; 61 u32 gpio1h_smt; 62 u32 gpio2l_smt; 63 u32 gpio2h_smt; 64 u32 gpio3l_smt; 65 u32 gpio3h_smt; 66 u32 reserved5[24]; 67 u32 soc_con0; 68 u32 soc_con1; 69 u32 soc_con2; 70 u32 soc_con3; 71 u32 soc_con4; 72 u32 soc_con5; 73 u32 soc_con6; 74 u32 soc_con7; 75 u32 soc_con8; 76 u32 soc_con9; 77 u32 soc_con10; 78 u32 soc_con11; 79 u32 reserved6[20]; 80 u32 soc_status0; 81 u32 soc_status1; 82 u32 reserved7[30]; 83 u32 cpu_con0; 84 u32 cpu_con1; 85 u32 reserved8[30]; 86 u32 os_reg0; 87 u32 os_reg1; 88 u32 os_reg2; 89 u32 os_reg3; 90 u32 reserved9[29]; 91 u32 ddr_status; 92 u32 reserved10[30]; 93 u32 sig_det_con; 94 u32 reserved11[3]; 95 u32 sig_det_status; 96 u32 reserved12[3]; 97 u32 sig_det_clr; 98 u32 reserved13[23]; 99 u32 host_con0; 100 u32 host_con1; 101 u32 reserved14[2]; 102 u32 dma_con0; 103 u32 dma_con1; 104 u32 reserved15[539]; 105 u32 uoc_status; 106 u32 host_status; 107 u32 gmac_con0; 108 u32 chip_id; 109 }; 110 check_member(rv1108_grf, chip_id, 0xf90); 111 112 struct rv1108_pmu_grf { 113 u32 gpioa_iomux; 114 u32 gpiob_iomux; 115 u32 gpioc_iomux; 116 u32 reserved1; 117 u32 gpioa_p; 118 u32 gpiob_p; 119 u32 gpioc_p; 120 u32 reserved2; 121 u32 gpioa_e; 122 u32 gpiob_e; 123 u32 gpioc_e; 124 u32 reserved3; 125 u32 gpioa_smt; 126 u32 gpiob_smt; 127 u32 gpioc_smt; 128 u32 reserved4; 129 u32 gpio0a_sr; 130 u32 gpio0b_sr; 131 u32 gpio0c_sr; 132 u32 reserved5[(0x100-0x4c)/4]; 133 u32 soc_con[4]; 134 u32 reserved6[(0x180-0x110)/4]; 135 u32 dll_con[2]; 136 u32 reserved7[2]; 137 u32 dll_status[2]; 138 u32 reserved8[(0x200-0x198)/4]; 139 u32 os_reg[4]; 140 u32 reserved9[(0x300-0x210)/4]; 141 u32 fast_boot_addr; 142 u32 reserved10[(0x380-0x304)/4]; 143 u32 a7_jtag_mask; 144 u32 reserved11[(0x388-0x384)/4]; 145 u32 ceva_jtag_mask; 146 }; 147 check_member(rv1108_pmu_grf, ceva_jtag_mask, 0x388); 148 149 /* GRF_GPIO1B_IOMUX */ 150 enum { 151 GPIO1B7_SHIFT = 14, 152 GPIO1B7_MASK = 3 << GPIO1B7_SHIFT, 153 GPIO1B7_GPIO = 0, 154 GPIO1B7_LCDC_D12, 155 GPIO1B7_I2S_SDIO2_M0, 156 GPIO1B7_GMAC_RXDV, 157 158 GPIO1B6_SHIFT = 12, 159 GPIO1B6_MASK = 3 << GPIO1B6_SHIFT, 160 GPIO1B6_GPIO = 0, 161 GPIO1B6_LCDC_D13, 162 GPIO1B6_I2S_LRCLKTX_M0, 163 GPIO1B6_GMAC_RXD1, 164 165 GPIO1B5_SHIFT = 10, 166 GPIO1B5_MASK = 3 << GPIO1B5_SHIFT, 167 GPIO1B5_GPIO = 0, 168 GPIO1B5_LCDC_D14, 169 GPIO1B5_I2S_SDIO1_M0, 170 GPIO1B5_GMAC_RXD0, 171 172 GPIO1B4_SHIFT = 8, 173 GPIO1B4_MASK = 3 << GPIO1B4_SHIFT, 174 GPIO1B4_GPIO = 0, 175 GPIO1B4_LCDC_D15, 176 GPIO1B4_I2S_MCLK_M0, 177 GPIO1B4_GMAC_TXEN, 178 179 GPIO1B3_SHIFT = 6, 180 GPIO1B3_MASK = 3 << GPIO1B3_SHIFT, 181 GPIO1B3_GPIO = 0, 182 GPIO1B3_LCDC_D16, 183 GPIO1B3_I2S_SCLK_M0, 184 GPIO1B3_GMAC_TXD1, 185 186 GPIO1B2_SHIFT = 4, 187 GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, 188 GPIO1B2_GPIO = 0, 189 GPIO1B2_LCDC_D17, 190 GPIO1B2_I2S_SDIO_M0, 191 GPIO1B2_GMAC_TXD0, 192 193 GPIO1B1_SHIFT = 2, 194 GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, 195 GPIO1B1_GPIO = 0, 196 GPIO1B1_LCDC_D9, 197 GPIO1B1_PWM7, 198 199 GPIO1B0_SHIFT = 0, 200 GPIO1B0_MASK = 3, 201 GPIO1B0_GPIO = 0, 202 GPIO1B0_LCDC_D8, 203 GPIO1B0_PWM6, 204 }; 205 206 /* GRF_GPIO1C_IOMUX */ 207 enum { 208 GPIO1C7_SHIFT = 14, 209 GPIO1C7_MASK = 3 << GPIO1C7_SHIFT, 210 GPIO1C7_GPIO = 0, 211 GPIO1C7_CIF_D5, 212 GPIO1C7_I2S_SDIO2_M1, 213 214 GPIO1C6_SHIFT = 12, 215 GPIO1C6_MASK = 3 << GPIO1C6_SHIFT, 216 GPIO1C6_GPIO = 0, 217 GPIO1C6_CIF_D4, 218 GPIO1C6_I2S_LRCLKTX_M1, 219 220 GPIO1C5_SHIFT = 10, 221 GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, 222 GPIO1C5_GPIO = 0, 223 GPIO1C5_LCDC_CLK, 224 GPIO1C5_GMAC_CLK, 225 226 GPIO1C4_SHIFT = 8, 227 GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, 228 GPIO1C4_GPIO = 0, 229 GPIO1C4_LCDC_HSYNC, 230 GPIO1C4_GMAC_MDC, 231 232 GPIO1C3_SHIFT = 6, 233 GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, 234 GPIO1C3_GPIO = 0, 235 GPIO1C3_LCDC_VSYNC, 236 GPIO1C3_GMAC_MDIO, 237 238 GPIO1C2_SHIFT = 4, 239 GPIO1C2_MASK = 3 << GPIO1C2_SHIFT, 240 GPIO1C2_GPIO = 0, 241 GPIO1C2_LCDC_EN, 242 GPIO1C2_I2S_SDIO3_M0, 243 GPIO1C2_GMAC_RXER, 244 245 GPIO1C1_SHIFT = 2, 246 GPIO1C1_MASK = 3 << GPIO1C1_SHIFT, 247 GPIO1C1_GPIO = 0, 248 GPIO1C1_LCDC_D10, 249 GPIO1C1_I2S_SDI_M0, 250 GPIO1C1_PWM4, 251 252 GPIO1C0_SHIFT = 0, 253 GPIO1C0_MASK = 3, 254 GPIO1C0_GPIO = 0, 255 GPIO1C0_LCDC_D11, 256 GPIO1C0_I2S_LRCLKRX_M0, 257 }; 258 259 /* GRF_GPIO1D_OIMUX */ 260 enum { 261 GPIO1D7_SHIFT = 14, 262 GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, 263 GPIO1D7_GPIO = 0, 264 GPIO1D7_HDMI_CEC, 265 GPIO1D7_DSP_RTCK, 266 267 GPIO1D6_SHIFT = 12, 268 GPIO1D6_MASK = 1 << GPIO1D6_SHIFT, 269 GPIO1D6_GPIO = 0, 270 GPIO1D6_HDMI_HPD_M0, 271 272 GPIO1D5_SHIFT = 10, 273 GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, 274 GPIO1D5_GPIO = 0, 275 GPIO1D5_UART2_RTSN, 276 GPIO1D5_HDMI_SDA_M0, 277 278 GPIO1D4_SHIFT = 8, 279 GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, 280 GPIO1D4_GPIO = 0, 281 GPIO1D4_UART2_CTSN, 282 GPIO1D4_HDMI_SCL_M0, 283 284 GPIO1D3_SHIFT = 6, 285 GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, 286 GPIO1D3_GPIO = 0, 287 GPIO1D3_UART0_SOUT, 288 GPIO1D3_SPI_TXD_M0, 289 290 GPIO1D2_SHIFT = 4, 291 GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, 292 GPIO1D2_GPIO = 0, 293 GPIO1D2_UART0_SIN, 294 GPIO1D2_SPI_RXD_M0, 295 GPIO1D2_DSP_TDI, 296 297 GPIO1D1_SHIFT = 2, 298 GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, 299 GPIO1D1_GPIO = 0, 300 GPIO1D1_UART0_RTSN, 301 GPIO1D1_SPI_CSN0_M0, 302 GPIO1D1_DSP_TMS, 303 304 GPIO1D0_SHIFT = 0, 305 GPIO1D0_MASK = 3, 306 GPIO1D0_GPIO = 0, 307 GPIO1D0_UART0_CTSN, 308 GPIO1D0_SPI_CLK_M0, 309 GPIO1D0_DSP_TCK, 310 }; 311 312 /* GRF_GPIO2A_IOMUX */ 313 enum { 314 GPIO2A7_SHIFT = 14, 315 GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, 316 GPIO2A7_GPIO = 0, 317 GPIO2A7_FLASH_D7, 318 GPIO2A7_EMMC_D7, 319 320 GPIO2A6_SHIFT = 12, 321 GPIO2A6_MASK = 3 << GPIO2A6_SHIFT, 322 GPIO2A6_GPIO = 0, 323 GPIO2A6_FLASH_D6, 324 GPIO2A6_EMMC_D6, 325 326 GPIO2A5_SHIFT = 10, 327 GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, 328 GPIO2A5_GPIO = 0, 329 GPIO2A5_FLASH_D5, 330 GPIO2A5_EMMC_D5, 331 332 GPIO2A4_SHIFT = 8, 333 GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, 334 GPIO2A4_GPIO = 0, 335 GPIO2A4_FLASH_D4, 336 GPIO2A4_EMMC_D4, 337 338 GPIO2A3_SHIFT = 6, 339 GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, 340 GPIO2A3_GPIO = 0, 341 GPIO2A3_FLASH_D3, 342 GPIO2A3_EMMC_D3, 343 GPIO2A3_SFC_HOLD_IO3, 344 345 GPIO2A2_SHIFT = 4, 346 GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, 347 GPIO2A2_GPIO = 0, 348 GPIO2A2_FLASH_D2, 349 GPIO2A2_EMMC_D2, 350 GPIO2A2_SFC_WP_IO2, 351 352 GPIO2A1_SHIFT = 2, 353 GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, 354 GPIO2A1_GPIO = 0, 355 GPIO2A1_FLASH_D1, 356 GPIO2A1_EMMC_D1, 357 GPIO2A1_SFC_SO_IO1, 358 359 GPIO2A0_SHIFT = 0, 360 GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, 361 GPIO2A0_GPIO = 0, 362 GPIO2A0_FLASH_D0, 363 GPIO2A0_EMMC_D0, 364 GPIO2A0_SFC_SI_IO0, 365 }; 366 367 /* GRF_GPIO2B_IOMUX */ 368 enum { 369 GPIO2B7_SHIFT = 14, 370 GPIO2B7_MASK = 3 << GPIO2B7_SHIFT, 371 GPIO2B7_GPIO = 0, 372 GPIO2B7_FLASH_CS1, 373 GPIO2B7_SFC_CLK, 374 375 GPIO2B6_SHIFT = 12, 376 GPIO2B6_MASK = 1 << GPIO2B6_SHIFT, 377 GPIO2B6_GPIO = 0, 378 GPIO2B6_EMMC_CLKO, 379 380 GPIO2B5_SHIFT = 10, 381 GPIO2B5_MASK = 1 << GPIO2B5_SHIFT, 382 GPIO2B5_GPIO = 0, 383 GPIO2B5_FLASH_CS0, 384 385 GPIO2B4_SHIFT = 8, 386 GPIO2B4_MASK = 3 << GPIO2B4_SHIFT, 387 GPIO2B4_GPIO = 0, 388 GPIO2B4_FLASH_RDY, 389 GPIO2B4_EMMC_CMD, 390 GPIO2B4_SFC_CSN0, 391 392 GPIO2B3_SHIFT = 6, 393 GPIO2B3_MASK = 1 << GPIO2B3_SHIFT, 394 GPIO2B3_GPIO = 0, 395 GPIO2B3_FLASH_RDN, 396 397 GPIO2B2_SHIFT = 4, 398 GPIO2B2_MASK = 1 << GPIO2B2_SHIFT, 399 GPIO2B2_GPIO = 0, 400 GPIO2B2_FLASH_WRN, 401 402 GPIO2B1_SHIFT = 2, 403 GPIO2B1_MASK = 1 << GPIO2B1_SHIFT, 404 GPIO2B1_GPIO = 0, 405 GPIO2B1_FLASH_CLE, 406 407 GPIO2B0_SHIFT = 0, 408 GPIO2B0_MASK = 1 << GPIO2B0_SHIFT, 409 GPIO2B0_GPIO = 0, 410 GPIO2B0_FLASH_ALE, 411 }; 412 413 /* GRF_GPIO2D_IOMUX */ 414 enum { 415 GPIO2D7_SHIFT = 14, 416 GPIO2D7_MASK = 1 << GPIO2D7_SHIFT, 417 GPIO2D7_GPIO = 0, 418 GPIO2D7_SDIO_D0, 419 420 GPIO2D6_SHIFT = 12, 421 GPIO2D6_MASK = 1 << GPIO2D6_SHIFT, 422 GPIO2D6_GPIO = 0, 423 GPIO2D6_SDIO_CMD, 424 425 GPIO2D5_SHIFT = 10, 426 GPIO2D5_MASK = 1 << GPIO2D5_SHIFT, 427 GPIO2D5_GPIO = 0, 428 GPIO2D5_SDIO_CLKO, 429 430 GPIO2D4_SHIFT = 8, 431 GPIO2D4_MASK = 1 << GPIO2D4_SHIFT, 432 GPIO2D4_GPIO = 0, 433 GPIO2D4_I2C1_SCL, 434 435 GPIO2D3_SHIFT = 6, 436 GPIO2D3_MASK = 1 << GPIO2D3_SHIFT, 437 GPIO2D3_GPIO = 0, 438 GPIO2D3_I2C1_SDA, 439 440 GPIO2D2_SHIFT = 4, 441 GPIO2D2_MASK = 3 << GPIO2D2_SHIFT, 442 GPIO2D2_GPIO = 0, 443 GPIO2D2_UART2_SOUT_M0, 444 GPIO2D2_JTAG_TCK, 445 446 GPIO2D1_SHIFT = 2, 447 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, 448 GPIO2D1_GPIO = 0, 449 GPIO2D1_UART2_SIN_M0, 450 GPIO2D1_JTAG_TMS, 451 GPIO2D1_DSP_TMS, 452 453 GPIO2D0_SHIFT = 0, 454 GPIO2D0_MASK = 3, 455 GPIO2D0_GPIO = 0, 456 GPIO2D0_UART0_CTSN, 457 GPIO2D0_SPI_CLK_M0, 458 GPIO2D0_DSP_TCK, 459 }; 460 461 /* GRF_GPIO3A_IOMUX */ 462 enum { 463 GPIO3A7_SHIFT = 14, 464 GPIO3A7_MASK = 1 << GPIO3A7_SHIFT, 465 GPIO3A7_GPIO = 0, 466 467 GPIO3A6_SHIFT = 12, 468 GPIO3A6_MASK = 3 << GPIO3A6_SHIFT, 469 GPIO3A6_GPIO = 0, 470 GPIO3A6_UART1_SOUT, 471 472 GPIO3A5_SHIFT = 10, 473 GPIO3A5_MASK = 3 << GPIO3A5_SHIFT, 474 GPIO3A5_GPIO = 0, 475 GPIO3A5_UART1_SIN, 476 477 GPIO3A4_SHIFT = 8, 478 GPIO3A4_MASK = 1 << GPIO3A4_SHIFT, 479 GPIO3A4_GPIO = 0, 480 GPIO3A4_UART1_CTSN, 481 482 GPIO3A3_SHIFT = 6, 483 GPIO3A3_MASK = 1 << GPIO3A3_SHIFT, 484 GPIO3A3_GPIO = 0, 485 GPIO3A3_UART1_RTSN, 486 487 GPIO3A2_SHIFT = 4, 488 GPIO3A2_MASK = 1 << GPIO3A2_SHIFT, 489 GPIO3A2_GPIO = 0, 490 GPIO3A2_SDIO_D3, 491 492 GPIO3A1_SHIFT = 2, 493 GPIO3A1_MASK = 1 << GPIO3A1_SHIFT, 494 GPIO3A1_GPIO = 0, 495 GPIO3A1_SDIO_D2, 496 497 GPIO3A0_SHIFT = 0, 498 GPIO3A0_MASK = 1, 499 GPIO3A0_GPIO = 0, 500 GPIO3A0_SDIO_D1, 501 }; 502 503 /* GRF_GPIO3C_IOMUX */ 504 enum { 505 GPIO3C7_SHIFT = 14, 506 GPIO3C7_MASK = 1 << GPIO3C7_SHIFT, 507 GPIO3C7_GPIO = 0, 508 GPIO3C7_CIF_CLKI, 509 510 GPIO3C6_SHIFT = 12, 511 GPIO3C6_MASK = 1 << GPIO3C6_SHIFT, 512 GPIO3C6_GPIO = 0, 513 GPIO3C6_CIF_VSYNC, 514 515 GPIO3C5_SHIFT = 10, 516 GPIO3C5_MASK = 1 << GPIO3C5_SHIFT, 517 GPIO3C5_GPIO = 0, 518 GPIO3C5_SDMMC_CMD, 519 520 GPIO3C4_SHIFT = 8, 521 GPIO3C4_MASK = 1 << GPIO3C4_SHIFT, 522 GPIO3C4_GPIO = 0, 523 GPIO3C4_SDMMC_CLKO, 524 525 GPIO3C3_SHIFT = 6, 526 GPIO3C3_MASK = 3 << GPIO3C3_SHIFT, 527 GPIO3C3_GPIO = 0, 528 GPIO3C3_SDMMC_D0, 529 GPIO3C3_UART2_SOUT_M1, 530 531 GPIO3C2_SHIFT = 4, 532 GPIO3C2_MASK = 3 << GPIO3C2_SHIFT, 533 GPIO3C2_GPIO = 0, 534 GPIO3C2_SDMMC_D1, 535 GPIO3C2_UART2_SIN_M1, 536 537 GPIOC1_SHIFT = 2, 538 GPIOC1_MASK = 1 << GPIOC1_SHIFT, 539 GPIOC1_GPIO = 0, 540 GPIOC1_SDMMC_D2, 541 542 GPIOC0_SHIFT = 0, 543 GPIOC0_MASK = 1, 544 GPIO3C0_GPIO = 0, 545 GPIO3C0_SDMMC_D3, 546 }; 547 548 enum { 549 /* GRF_SOC_CON0 */ 550 MSCH_MAINDDR3_SHIFT = 4, 551 MSCH_MAINDDR3 = 1 << MSCH_MAINDDR3_SHIFT, 552 MSCH_MAINPARTIALPOP_SHIFT = 5, 553 MSCH_MAINPARTIALPOP = 1 << MSCH_MAINPARTIALPOP_SHIFT, 554 MSCH_MAINPARTIALPOP_MASK = 1 << MSCH_MAINPARTIALPOP_SHIFT, 555 }; 556 557 enum { 558 /* PMU_GRF_SOC_CON0 */ 559 DDRPHY_BUFFEREN_CORE_SHIFT = 2, 560 DDRPHY_BUFFEREN_CORE_MASK = 1 << DDRPHY_BUFFEREN_CORE_SHIFT, 561 DDRPHY_BUFFEREN_CORE_EN = 1 << DDRPHY_BUFFEREN_CORE_SHIFT, 562 }; 563 #endif 564