1 /* 2 * (C) Copyright 2022 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_GRF_RK3528_H 7 #define _ASM_ARCH_GRF_RK3528_H 8 9 #include <common.h> 10 11 struct rk3528_grf { 12 uint32_t reserved0[0x60028 / 4]; 13 14 /* vogrf */ 15 uint32_t sdmmc_con1; /* Address Offset: 0x60028 */ 16 uint32_t reserved1[(0x70000 - 0x60028) / 4 - 1]; 17 18 /* pmugrf */ 19 uint32_t soc_con[8]; /* Address Offset: 0x70000 */ 20 uint32_t soc_status; /* Address Offset: 0x70020 */ 21 uint32_t reserved3[3]; /* Address Offset: 0x70024 */ 22 uint32_t pmuio_vsel; /* Address Offset: 0x70030 */ 23 uint32_t reserved4[3]; /* Address Offset: 0x70034 */ 24 uint32_t mem_con; /* Address Offset: 0x70040 */ 25 uint32_t reserved5[47]; /* Address Offset: 0x70044 */ 26 uint32_t rstfunc_status; /* Address Offset: 0x70100 */ 27 uint32_t rstfunc_clr; /* Address Offset: 0x70104 */ 28 uint32_t reserved6[62]; /* Address Offset: 0x70108 */ 29 uint32_t os_reg0; /* Address Offset: 0x70200 */ 30 uint32_t os_reg1; /* Address Offset: 0x70204 */ 31 uint32_t os_reg2; /* Address Offset: 0x70208 */ 32 uint32_t os_reg3; /* Address Offset: 0x7020C */ 33 uint32_t os_reg4; /* Address Offset: 0x70210 */ 34 uint32_t os_reg5; /* Address Offset: 0x70214 */ 35 uint32_t os_reg6; /* Address Offset: 0x70218 */ 36 uint32_t os_reg7; /* Address Offset: 0x7021C */ 37 uint32_t os_reg8; /* Address Offset: 0x70220 */ 38 uint32_t os_reg9; /* Address Offset: 0x70224 */ 39 uint32_t os_reg10; /* Address Offset: 0x70228 */ 40 uint32_t os_reg11; /* Address Offset: 0x7022C */ 41 uint32_t os_reg12; /* Address Offset: 0x70230 */ 42 uint32_t os_reg13; /* Address Offset: 0x70234 */ 43 uint32_t os_reg14; /* Address Offset: 0x70238 */ 44 uint32_t os_reg15; /* Address Offset: 0x7023C */ 45 uint32_t os_reg16; /* Address Offset: 0x70240 */ 46 uint32_t os_reg17; /* Address Offset: 0x70244 */ 47 uint32_t os_reg18; /* Address Offset: 0x70248 */ 48 uint32_t os_reg19; /* Address Offset: 0x7024C */ 49 uint32_t os_reg20; /* Address Offset: 0x70250 */ 50 uint32_t os_reg21; /* Address Offset: 0x70254 */ 51 uint32_t os_reg22; /* Address Offset: 0x70258 */ 52 uint32_t os_reg23; /* Address Offset: 0x7025C */ 53 uint32_t reserved7[(0x80000 - 0x7025C) / 4 - 1]; 54 55 uint32_t grf_sys_con[2]; /* Address Offset: 0x80000 */ 56 uint32_t reserved8[2]; /* Address Offset: 0x80008 */ 57 uint32_t grf_sys_status; /* Address Offset: 0x80010 */ 58 uint32_t reserved9[3]; /* Address Offset: 0x80014 */ 59 uint32_t grf_biu_con[2]; /* Address Offset: 0x80020 */ 60 uint32_t reserved10[2]; /* Address Offset: 0x80028 */ 61 uint32_t grf_biu_status[3]; /* Address Offset: 0x80030 */ 62 uint32_t reserved11[17]; /* Address Offset: 0x8003C */ 63 uint32_t grf_sys_mem_con[5]; /* Address Offset: 0x80080 */ 64 uint32_t reserved12[59]; /* Address Offset: 0x80094 */ 65 uint32_t grf_soc_code; /* Address Offset: 0x80180 */ 66 uint32_t reserved13[3]; /* Address Offset: 0x80184 */ 67 uint32_t grf_soc_version; /* Address Offset: 0x80190 */ 68 uint32_t reserved14[3]; /* Address Offset: 0x80194 */ 69 uint32_t grf_chip_id; /* Address Offset: 0x801A0 */ 70 uint32_t reserved15[3]; /* Address Offset: 0x801A4 */ 71 uint32_t grf_chip_version; /* Address Offset: 0x801B0 */ 72 uint32_t reserved16[(0x10000 - 0x81b0) / 4 - 1]; 73 74 }; 75 76 check_member(rk3528_grf, sdmmc_con1, 0x60028); 77 check_member(rk3528_grf, os_reg23, 0x7025C); 78 check_member(rk3528_grf, grf_chip_version, 0x801B0); 79 80 #endif 81