1 /* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 #ifndef _ASM_ARCH_GRF_RK3368_H 8 #define _ASM_ARCH_GRF_RK3368_H 9 10 #include <common.h> 11 12 struct rk3368_grf { 13 u32 gpio1a_iomux; 14 u32 gpio1b_iomux; 15 u32 gpio1c_iomux; 16 u32 gpio1d_iomux; 17 u32 gpio2a_iomux; 18 u32 gpio2b_iomux; 19 u32 gpio2c_iomux; 20 u32 gpio2d_iomux; 21 u32 gpio3a_iomux; 22 u32 gpio3b_iomux; 23 u32 gpio3c_iomux; 24 u32 gpio3d_iomux; 25 u32 reserved[0x34]; 26 u32 gpio1a_pull; 27 u32 gpio1b_pull; 28 u32 gpio1c_pull; 29 u32 gpio1d_pull; 30 u32 gpio2a_pull; 31 u32 gpio2b_pull; 32 u32 gpio2c_pull; 33 u32 gpio2d_pull; 34 u32 gpio3a_pull; 35 u32 gpio3b_pull; 36 u32 gpio3c_pull; 37 u32 gpio3d_pull; 38 u32 reserved1[0x34]; 39 u32 gpio1a_drv; 40 u32 gpio1b_drv; 41 u32 gpio1c_drv; 42 u32 gpio1d_drv; 43 u32 gpio2a_drv; 44 u32 gpio2b_drv; 45 u32 gpio2c_drv; 46 u32 gpio2d_drv; 47 u32 gpio3a_drv; 48 u32 gpio3b_drv; 49 u32 gpio3c_drv; 50 u32 gpio3d_drv; 51 u32 reserved2[0x34]; 52 u32 gpio1l_sr; 53 u32 gpio1h_sr; 54 u32 gpio2l_sr; 55 u32 gpio2h_sr; 56 u32 gpio3l_sr; 57 u32 gpio3h_sr; 58 u32 reserved3[0x1a]; 59 u32 gpio_smt; 60 u32 reserved4[0x1f]; 61 u32 soc_con0; 62 u32 soc_con1; 63 u32 soc_con2; 64 u32 soc_con3; 65 u32 soc_con4; 66 u32 soc_con5; 67 u32 soc_con6; 68 u32 soc_con7; 69 u32 soc_con8; 70 u32 soc_con9; 71 u32 soc_con10; 72 u32 soc_con11; 73 u32 soc_con12; 74 u32 soc_con13; 75 u32 soc_con14; 76 u32 soc_con15; 77 u32 soc_con16; 78 u32 soc_con17; 79 }; 80 check_member(rk3368_grf, soc_con17, 0x444); 81 82 struct rk3368_pmu_grf { 83 u32 gpio0a_iomux; 84 u32 gpio0b_iomux; 85 u32 gpio0c_iomux; 86 u32 gpio0d_iomux; 87 u32 gpio0a_pull; 88 u32 gpio0b_pull; 89 u32 gpio0c_pull; 90 u32 gpio0d_pull; 91 u32 gpio0a_drv; 92 u32 gpio0b_drv; 93 u32 gpio0c_drv; 94 u32 gpio0d_drv; 95 u32 gpio0l_sr; 96 u32 gpio0h_sr; 97 u32 reserved[0x72]; 98 u32 os_reg[4]; 99 }; 100 check_member(rk3368_pmu_grf, gpio0h_sr, 0x34); 101 check_member(rk3368_pmu_grf, os_reg[0], 0x200); 102 103 /*GRF_SOC_CON11/12/13*/ 104 enum { 105 MCU_SRAM_BASE_BIT27_BIT12_SHIFT = 0, 106 MCU_SRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0), 107 }; 108 109 /*GRF_SOC_CON12*/ 110 enum { 111 MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT = 0, 112 MCU_EXSRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0), 113 }; 114 115 /*GRF_SOC_CON13*/ 116 enum { 117 MCU_EXPERI_BASE_BIT27_BIT12_SHIFT = 0, 118 MCU_EXPERI_BASE_BIT27_BIT12_MASK = GENMASK(15, 0), 119 }; 120 121 /*GRF_SOC_CON14*/ 122 enum { 123 MCU_EXPERI_BASE_BIT31_BIT28_SHIFT = 12, 124 MCU_EXPERI_BASE_BIT31_BIT28_MASK = GENMASK(15, 12), 125 MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT = 8, 126 MCU_EXSRAM_BASE_BIT31_BIT28_MASK = GENMASK(11, 8), 127 MCU_SRAM_BASE_BIT31_BIT28_SHIFT = 4, 128 MCU_SRAM_BASE_BIT31_BIT28_MASK = GENMASK(7, 4), 129 MCU_CODE_BASE_BIT31_BIT28_SHIFT = 0, 130 MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0), 131 }; 132 133 #endif 134