1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_GRF_px30_H 7 #define _ASM_ARCH_GRF_px30_H 8 9 #include <common.h> 10 11 struct px30_grf { 12 unsigned int gpio1al_iomux; 13 unsigned int gpio1ah_iomux; 14 unsigned int gpio1bl_iomux; 15 unsigned int gpio1bh_iomux; 16 unsigned int gpio1cl_iomux; 17 unsigned int gpio1ch_iomux; 18 unsigned int gpio1dl_iomux; 19 unsigned int gpio1dh_iomux; 20 21 unsigned int gpio2al_iomux; 22 unsigned int gpio2ah_iomux; 23 unsigned int gpio2bl_iomux; 24 unsigned int gpio2bh_iomux; 25 unsigned int gpio2cl_iomux; 26 unsigned int gpio2ch_iomux; 27 unsigned int gpio2dl_iomux; 28 unsigned int gpio2dh_iomux; 29 30 unsigned int gpio3al_iomux; 31 unsigned int gpio3ah_iomux; 32 unsigned int gpio3bl_iomux; 33 unsigned int gpio3bh_iomux; 34 unsigned int gpio3cl_iomux; 35 unsigned int gpio3ch_iomux; 36 unsigned int gpio3dl_iomux; 37 unsigned int gpio3dh_iomux; 38 39 unsigned int gpio1a_p; 40 unsigned int gpio1b_p; 41 unsigned int gpio1c_p; 42 unsigned int gpio1d_p; 43 unsigned int gpio2a_p; 44 unsigned int gpio2b_p; 45 unsigned int gpio2c_p; 46 unsigned int gpio2d_p; 47 unsigned int gpio3a_p; 48 unsigned int gpio3b_p; 49 unsigned int gpio3c_p; 50 unsigned int gpio3d_p; 51 unsigned int gpio1a_sr; 52 unsigned int gpio1b_sr; 53 unsigned int gpio1c_sr; 54 unsigned int gpio1d_sr; 55 unsigned int gpio2a_sr; 56 unsigned int gpio2b_sr; 57 unsigned int gpio2c_sr; 58 unsigned int gpio2d_sr; 59 unsigned int gpio3a_sr; 60 unsigned int gpio3b_sr; 61 unsigned int gpio3c_sr; 62 unsigned int gpio3d_sr; 63 unsigned int gpio1a_smt; 64 unsigned int gpio1b_smt; 65 unsigned int gpio1c_smt; 66 unsigned int gpio1d_smt; 67 unsigned int gpio2a_smt; 68 unsigned int gpio2b_smt; 69 unsigned int gpio2c_smt; 70 unsigned int gpio2d_smt; 71 unsigned int gpio3a_smt; 72 unsigned int gpio3b_smt; 73 unsigned int gpio3c_smt; 74 unsigned int gpio3d_smt; 75 unsigned int gpio1a_e; 76 unsigned int gpio1b_e; 77 unsigned int gpio1c_e; 78 unsigned int gpio1d_e; 79 unsigned int gpio2a_e; 80 unsigned int gpio2b_e; 81 unsigned int gpio2c_e; 82 unsigned int gpio2d_e; 83 unsigned int gpio3a_e; 84 unsigned int gpio3b_e; 85 unsigned int gpio3c_e; 86 unsigned int gpio3d_e; 87 88 unsigned int reserved0[(0x180 - 0x11C) / 4 - 1]; 89 unsigned int io_vsel; 90 unsigned int iofunc_con0; 91 unsigned int reserved1[(0x400 - 0x184) / 4 - 1]; 92 unsigned int soc_con[6]; 93 unsigned int reserved2[(0x480 - 0x414) / 4 - 1]; 94 unsigned int soc_status0; 95 unsigned int reserved3[(0x500 - 0x480) / 4 - 1]; 96 unsigned int cpu_con[3]; 97 unsigned int reserved4[5]; 98 unsigned int cpu_status[2]; 99 unsigned int reserved5[2]; 100 unsigned int soc_noc_con[2]; 101 unsigned int reserved6[6]; 102 unsigned int ddr_bankhash[4]; 103 unsigned int reserved7[(0x700 - 0x55c) / 4 - 1]; 104 unsigned int host0_con[2]; 105 unsigned int reserved8[(0x880 - 0x704) / 4 - 1]; 106 unsigned int otg_con3; 107 unsigned int reserved9[3]; 108 unsigned int host0_status4; 109 unsigned int reserved10[(0x904 - 0x890) / 4 - 1]; 110 unsigned int mac_con1; 111 }; 112 113 check_member(px30_grf, mac_con1, 0x904); 114 115 struct px30_pmugrf { 116 unsigned int gpio0a_e; 117 unsigned int gpio0b_e; 118 unsigned int gpio0c_e; 119 unsigned int gpio0d_e; 120 unsigned int gpio0a_p; 121 unsigned int gpio0b_p; 122 unsigned int gpio0c_p; 123 unsigned int gpio0d_p; 124 unsigned int gpio0al_iomux; 125 unsigned int gpio0bl_iomux; 126 unsigned int gpio0cl_iomux; 127 unsigned int gpio0dl_iomux; 128 unsigned int gpio0l_sr; 129 unsigned int gpio0h_sr; 130 unsigned int gpio0l_smt; 131 unsigned int gpio0h_smt; 132 unsigned int reserved1[(0x100 - 0x3c) / 4 - 1]; 133 unsigned int soc_con[4]; 134 unsigned int reserved2[(0x180 - 0x10c) / 4 - 1]; 135 unsigned int pvtm_con[2]; 136 unsigned int reserved3[2]; 137 unsigned int pvtm_status[2]; 138 unsigned int reserved4[(0x200 - 0x194) / 4 - 1]; 139 unsigned int os_reg[12]; 140 unsigned int reset_function_status; 141 }; 142 143 check_member(px30_pmugrf, reset_function_status, 0x230); 144 145 /* GRF_GPIO0A_IOMUX */ 146 enum { 147 GPIO0A7_SHIFT = 14, 148 GPIO0A7_MASK = 3 << GPIO0A7_SHIFT, 149 GPIO0A7_GPIO = 0, 150 GPIO0A7_I2C3_SDA, 151 GPIO0A7_HDMI_DDCSDA, 152 153 GPIO0A6_SHIFT = 12, 154 GPIO0A6_MASK = 3 << GPIO0A6_SHIFT, 155 GPIO0A6_GPIO = 0, 156 GPIO0A6_I2C3_SCL, 157 GPIO0A6_HDMI_DDCSCL, 158 159 GPIO0A3_SHIFT = 6, 160 GPIO0A3_MASK = 3 << GPIO0A3_SHIFT, 161 GPIO0A3_GPIO = 0, 162 GPIO0A3_I2C1_SDA, 163 GPIO0A3_SDIO_CMD, 164 165 GPIO0A2_SHIFT = 4, 166 GPIO0A2_MASK = 3 << GPIO0A2_SHIFT, 167 GPIO0A2_GPIO = 0, 168 GPIO0A2_I2C1_SCL, 169 170 GPIO0A1_SHIFT = 2, 171 GPIO0A1_MASK = 3 << GPIO0A1_SHIFT, 172 GPIO0A1_GPIO = 0, 173 GPIO0A1_I2C0_SDA, 174 175 GPIO0A0_SHIFT = 0, 176 GPIO0A0_MASK = 3 << GPIO0A0_SHIFT, 177 GPIO0A0_GPIO = 0, 178 GPIO0A0_I2C0_SCL, 179 }; 180 181 /* GRF_GPIO0B_IOMUX */ 182 enum { 183 GPIO0B7_SHIFT = 14, 184 GPIO0B7_MASK = 3 << GPIO0B7_SHIFT, 185 GPIO0B7_GPIO = 0, 186 GPIO0B7_HDMI_HDP, 187 188 GPIO0B6_SHIFT = 12, 189 GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, 190 GPIO0B6_GPIO = 0, 191 GPIO0B6_I2S_SDI, 192 GPIO0B6_SPI_CSN0, 193 194 GPIO0B5_SHIFT = 10, 195 GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, 196 GPIO0B5_GPIO = 0, 197 GPIO0B5_I2S_SDO, 198 GPIO0B5_SPI_RXD, 199 200 GPIO0B3_SHIFT = 6, 201 GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, 202 GPIO0B3_GPIO = 0, 203 GPIO0B3_I2S1_LRCKRX, 204 GPIO0B3_SPI_TXD, 205 206 GPIO0B1_SHIFT = 2, 207 GPIO0B1_MASK = 3 << GPIO0B1_SHIFT, 208 GPIO0B1_GPIO = 0, 209 GPIO0B1_I2S_SCLK, 210 GPIO0B1_SPI_CLK, 211 212 GPIO0B0_SHIFT = 0, 213 GPIO0B0_MASK = 3, 214 GPIO0B0_GPIO = 0, 215 GPIO0B0_I2S_MCLK, 216 }; 217 218 /* GRF_GPIO0C_IOMUX */ 219 enum { 220 GPIO0C4_SHIFT = 8, 221 GPIO0C4_MASK = 3 << GPIO0C4_SHIFT, 222 GPIO0C4_GPIO = 0, 223 GPIO0C4_HDMI_CECSDA, 224 225 GPIO0C1_SHIFT = 2, 226 GPIO0C1_MASK = 3 << GPIO0C1_SHIFT, 227 GPIO0C1_GPIO = 0, 228 GPIO0C1_UART0_RSTN, 229 GPIO0C1_CLK_OUT1, 230 }; 231 232 /* GRF_GPIO0D_IOMUX */ 233 enum { 234 GPIO0D6_SHIFT = 12, 235 GPIO0D6_MASK = 3 << GPIO0D6_SHIFT, 236 GPIO0D6_GPIO = 0, 237 GPIO0D6_SDIO_PWREN, 238 GPIO0D6_PWM11, 239 240 241 GPIO0D4_SHIFT = 8, 242 GPIO0D4_MASK = 3 << GPIO0D4_SHIFT, 243 GPIO0D4_GPIO = 0, 244 GPIO0D4_PWM2, 245 246 GPIO0D3_SHIFT = 6, 247 GPIO0D3_MASK = 3 << GPIO0D3_SHIFT, 248 GPIO0D3_GPIO = 0, 249 GPIO0D3_PWM1, 250 251 GPIO0D2_SHIFT = 4, 252 GPIO0D2_MASK = 3 << GPIO0D2_SHIFT, 253 GPIO0D2_GPIO = 0, 254 GPIO0D2_PWM0, 255 }; 256 257 /* GRF_GPIO1A_IOMUX */ 258 enum { 259 GPIO1A7_SHIFT = 14, 260 GPIO1A7_MASK = 1, 261 GPIO1A7_GPIO = 0, 262 GPIO1A7_SDMMC_WRPRT, 263 }; 264 265 /* GRF_GPIO1B_IOMUX */ 266 enum { 267 GPIO1B7_SHIFT = 14, 268 GPIO1B7_MASK = 3 << GPIO1B7_SHIFT, 269 GPIO1B7_GPIO = 0, 270 GPIO1B7_SDMMC_CMD, 271 272 GPIO1B6_SHIFT = 12, 273 GPIO1B6_MASK = 3 << GPIO1B6_SHIFT, 274 GPIO1B6_GPIO = 0, 275 GPIO1B6_SDMMC_PWREN, 276 277 GPIO1B4_SHIFT = 8, 278 GPIO1B4_MASK = 3 << GPIO1B4_SHIFT, 279 GPIO1B4_GPIO = 0, 280 GPIO1B4_SPI_CSN1, 281 GPIO1B4_PWM12, 282 283 GPIO1B3_SHIFT = 6, 284 GPIO1B3_MASK = 3 << GPIO1B3_SHIFT, 285 GPIO1B3_GPIO = 0, 286 GPIO1B3_UART1_RSTN, 287 GPIO1B3_PWM13, 288 289 GPIO1B2_SHIFT = 4, 290 GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, 291 GPIO1B2_GPIO = 0, 292 GPIO1B2_UART1_SIN, 293 GPIO1B2_UART21_SIN, 294 295 GPIO1B1_SHIFT = 2, 296 GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, 297 GPIO1B1_GPIO = 0, 298 GPIO1B1_UART1_SOUT, 299 GPIO1B1_UART21_SOUT, 300 }; 301 302 /* GRF_GPIO1C_IOMUX */ 303 enum { 304 GPIO1C7_SHIFT = 14, 305 GPIO1C7_MASK = 3 << GPIO1C7_SHIFT, 306 GPIO1C7_GPIO = 0, 307 GPIO1C7_NAND_CS3, 308 GPIO1C7_EMMC_RSTNOUT, 309 310 GPIO1C6_SHIFT = 12, 311 GPIO1C6_MASK = 3 << GPIO1C6_SHIFT, 312 GPIO1C6_GPIO = 0, 313 GPIO1C6_NAND_CS2, 314 GPIO1C6_EMMC_CMD, 315 316 317 GPIO1C5_SHIFT = 10, 318 GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, 319 GPIO1C5_GPIO = 0, 320 GPIO1C5_SDMMC_D3, 321 GPIO1C5_JTAG_TMS, 322 323 GPIO1C4_SHIFT = 8, 324 GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, 325 GPIO1C4_GPIO = 0, 326 GPIO1C4_SDMMC_D2, 327 GPIO1C4_JTAG_TCK, 328 329 GPIO1C3_SHIFT = 6, 330 GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, 331 GPIO1C3_GPIO = 0, 332 GPIO1C3_SDMMC_D1, 333 GPIO1C3_UART2_SIN, 334 335 GPIO1C2_SHIFT = 4, 336 GPIO1C2_MASK = 3 << GPIO1C2_SHIFT , 337 GPIO1C2_GPIO = 0, 338 GPIO1C2_SDMMC_D0, 339 GPIO1C2_UART2_SOUT, 340 341 GPIO1C1_SHIFT = 2, 342 GPIO1C1_MASK = 3 << GPIO1C1_SHIFT, 343 GPIO1C1_GPIO = 0, 344 GPIO1C1_SDMMC_DETN, 345 346 GPIO1C0_SHIFT = 0, 347 GPIO1C0_MASK = 3 << GPIO1C0_SHIFT, 348 GPIO1C0_GPIO = 0, 349 GPIO1C0_SDMMC_CLKOUT, 350 }; 351 352 /* GRF_GPIO1DL_IOMUX */ 353 enum { 354 355 GPIO1D3_SHIFT = 12, 356 GPIO1D3_MASK = 0xf << GPIO1D3_SHIFT, 357 GPIO1D3_GPIO = 0, 358 GPIO1D3_SDMMC1_D1, 359 GPIO1D3_UART2_RXM0, 360 361 GPIO1D2_SHIFT = 8, 362 GPIO1D2_MASK = 0xf << GPIO1D2_SHIFT, 363 GPIO1D2_GPIO = 0, 364 GPIO1D2_SDMMC1_D0, 365 GPIO1D2_UART2_TXM0, 366 367 GPIO1D1_SHIFT = 4, 368 GPIO1D1_MASK = 0xf << GPIO1D1_SHIFT, 369 GPIO1D1_GPIO = 0, 370 GPIO1D1_SDMMC1_D3, 371 372 GPIO1D0_SHIFT = 0, 373 GPIO1D0_MASK = 0xf << GPIO1D0_SHIFT, 374 GPIO1D0_GPIO = 0, 375 GPIO1D0_SDMMC1_D2, 376 }; 377 /* GRF_GPIO1DH_IOMUX */ 378 enum { 379 380 GPIO1D7_SHIFT = 14, 381 GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, 382 GPIO1D7_GPIO = 0, 383 GPIO1D7_NAND_D7, 384 GPIO1D7_EMMC_D7, 385 386 GPIO1D6_SHIFT = 12, 387 GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, 388 GPIO1D6_GPIO = 0, 389 GPIO1D6_NAND_D6, 390 GPIO1D6_EMMC_D6, 391 392 GPIO1D5_SHIFT = 10, 393 GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, 394 GPIO1D5_GPIO = 0, 395 GPIO1D5_NAND_D5, 396 GPIO1D5_EMMC_D5, 397 398 GPIO1D4_SHIFT = 8, 399 GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, 400 GPIO1D4_GPIO = 0, 401 GPIO1D4_NAND_D4, 402 GPIO1D4_EMMC_D4, 403 }; 404 /* GRF_GPIO2A_IOMUX */ 405 enum { 406 GPIO2A7_SHIFT = 14, 407 GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, 408 GPIO2A7_GPIO = 0, 409 GPIO2A7_NAND_DQS, 410 GPIO2A7_EMMC_CLKOUT, 411 412 GPIO2A5_SHIFT = 10, 413 GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, 414 GPIO2A5_GPIO = 0, 415 GPIO2A5_NAND_WP, 416 GPIO2A5_EMMC_PWREN, 417 418 GPIO2A4_SHIFT = 8, 419 GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, 420 GPIO2A4_GPIO = 0, 421 GPIO2A4_NAND_RDY, 422 GPIO2A4_EMMC_CMD, 423 424 GPIO2A3_SHIFT = 6, 425 GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, 426 GPIO2A3_GPIO = 0, 427 GPIO2A3_NAND_RDN, 428 GPIO2A4_SPI1_CSN1, 429 430 GPIO2A2_SHIFT = 4, 431 GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, 432 GPIO2A2_GPIO = 0, 433 GPIO2A2_NAND_WRN, 434 GPIO2A4_SPI1_CSN0, 435 436 GPIO2A1_SHIFT = 2, 437 GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, 438 GPIO2A1_GPIO = 0, 439 GPIO2A1_NAND_CLE, 440 GPIO2A1_SPI1_TXD, 441 442 GPIO2A0_SHIFT = 0, 443 GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, 444 GPIO2A0_GPIO = 0, 445 GPIO2A0_NAND_ALE, 446 GPIO2A0_SPI1_RXD, 447 }; 448 449 /* GRF_GPIO2B_IOMUX */ 450 enum { 451 GPIO2B7_SHIFT = 14, 452 GPIO2B7_MASK = 3 << GPIO2B7_SHIFT, 453 GPIO2B7_GPIO = 0, 454 GPIO2B7_GMAC_RXER, 455 456 GPIO2B6_SHIFT = 12, 457 GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, 458 GPIO2B6_GPIO = 0, 459 GPIO2B6_GMAC_CLK, 460 GPIO2B6_MAC_LINK, 461 462 GPIO2B5_SHIFT = 10, 463 GPIO2B5_MASK = 3 << GPIO2B5_SHIFT, 464 GPIO2B5_GPIO = 0, 465 GPIO2B5_GMAC_TXEN, 466 467 GPIO2B4_SHIFT = 8, 468 GPIO2B4_MASK = 3 << GPIO2B4_SHIFT, 469 GPIO2B4_GPIO = 0, 470 GPIO2B4_GMAC_MDIO, 471 472 GPIO2B3_SHIFT = 6, 473 GPIO2B3_MASK = 3 << GPIO2B3_SHIFT, 474 GPIO2B3_GPIO = 0, 475 GPIO2B3_GMAC_RXCLK, 476 477 GPIO2B2_SHIFT = 4, 478 GPIO2B2_MASK = 3 << GPIO2B2_SHIFT, 479 GPIO2B2_GPIO = 0, 480 GPIO2B2_GMAC_CRS, 481 482 GPIO2B1_SHIFT = 2, 483 GPIO2B1_MASK = 3 << GPIO2B1_SHIFT, 484 GPIO2B1_GPIO = 0, 485 GPIO2B1_GMAC_TXCLK, 486 487 488 GPIO2B0_SHIFT = 0, 489 GPIO2B0_MASK = 3 << GPIO2B0_SHIFT, 490 GPIO2B0_GPIO = 0, 491 GPIO2B0_GMAC_RXDV, 492 GPIO2B0_MAC_SPEED_IOUT, 493 }; 494 495 /* GRF_GPIO2C_IOMUX */ 496 enum { 497 GPIO2C7_SHIFT = 14, 498 GPIO2C7_MASK = 3 << GPIO2C7_SHIFT, 499 GPIO2C7_GPIO = 0, 500 GPIO2C7_GMAC_TXD3, 501 502 GPIO2C6_SHIFT = 12, 503 GPIO2C6_MASK = 3 << GPIO2C6_SHIFT, 504 GPIO2C6_GPIO = 0, 505 GPIO2C6_GMAC_TXD2, 506 507 GPIO2C5_SHIFT = 10, 508 GPIO2C5_MASK = 3 << GPIO2C5_SHIFT, 509 GPIO2C5_GPIO = 0, 510 GPIO2C5_I2C2_SCL, 511 GPIO2C5_GMAC_RXD2, 512 513 GPIO2C4_SHIFT = 8, 514 GPIO2C4_MASK = 3 << GPIO2C4_SHIFT, 515 GPIO2C4_GPIO = 0, 516 GPIO2C4_I2C2_SDA, 517 GPIO2C4_GMAC_RXD3, 518 519 GPIO2C3_SHIFT = 6, 520 GPIO2C3_MASK = 3 << GPIO2C3_SHIFT, 521 GPIO2C3_GPIO = 0, 522 GPIO2C3_GMAC_TXD0, 523 524 GPIO2C2_SHIFT = 4, 525 GPIO2C2_MASK = 3 << GPIO2C2_SHIFT, 526 GPIO2C2_GPIO = 0, 527 GPIO2C2_GMAC_TXD1, 528 529 GPIO2C1_SHIFT = 2, 530 GPIO2C1_MASK = 3 << GPIO2C1_SHIFT, 531 GPIO2C1_GPIO = 0, 532 GPIO2C1_GMAC_RXD0, 533 534 GPIO2C0_SHIFT = 0, 535 GPIO2C0_MASK = 3 << GPIO2C0_SHIFT, 536 GPIO2C0_GPIO = 0, 537 GPIO2C0_GMAC_RXD1, 538 }; 539 540 /* GRF_GPIO2D_IOMUX */ 541 enum { 542 GPIO2D1_SHIFT = 2, 543 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, 544 GPIO2D1_GPIO = 0, 545 GPIO2D1_GMAC_MDC, 546 547 GPIO2D0_SHIFT = 0, 548 GPIO2D0_MASK = 3, 549 GPIO2D0_GPIO = 0, 550 GPIO2D0_GMAC_COL, 551 }; 552 553 /* GRF_GPIO3C_IOMUX */ 554 enum { 555 GPIO3C6_SHIFT = 12, 556 GPIO3C6_MASK = 3 << GPIO3C6_SHIFT, 557 GPIO3C6_GPIO = 0, 558 GPIO3C6_DRV_VBUS1, 559 560 GPIO3C5_SHIFT = 10, 561 GPIO3C5_MASK = 3 << GPIO3C5_SHIFT, 562 GPIO3C5_GPIO = 0, 563 GPIO3C5_PWM10, 564 565 GPIO3C1_SHIFT = 2, 566 GPIO3C1_MASK = 3 << GPIO3C1_SHIFT, 567 GPIO3C1_GPIO = 0, 568 GPIO3C1_DRV_VBUS, 569 }; 570 571 /* GRF_GPIO3D_IOMUX */ 572 enum { 573 GPIO3D2_SHIFT = 4, 574 GPIO3D2_MASK = 3 << GPIO3D2_SHIFT, 575 GPIO3D2_GPIO = 0, 576 GPIO3D2_PWM3, 577 }; 578 579 /* GRF_IOFUNC_CON0 */ 580 enum { 581 CON_IOMUX_UART2SEL_SHIFT = 10, 582 CON_IOMUX_UART2SEL_MASK = 3 << CON_IOMUX_UART2SEL_SHIFT, 583 CON_IOMUX_UART2SEL_M0 = 0, 584 CON_IOMUX_UART2SEL_M1, 585 CON_IOMUX_UART2SEL_USBPHY, 586 }; 587 588 /* GRF_MACPHY_CON0 */ 589 enum { 590 MACPHY_CFG_ENABLE_SHIFT = 0, 591 MACPHY_CFG_ENABLE_MASK = 1 << MACPHY_CFG_ENABLE_SHIFT, 592 }; 593 #endif 594