1*1f8f7730SSimon Glass /* 2*1f8f7730SSimon Glass * (C) Copyright 2015 Google, Inc 3*1f8f7730SSimon Glass * 4*1f8f7730SSimon Glass * SPDX-License-Identifier: GPL-2.0+ 5*1f8f7730SSimon Glass */ 6*1f8f7730SSimon Glass 7*1f8f7730SSimon Glass #ifndef _ASM_ARCH_GPIO_H 8*1f8f7730SSimon Glass #define _ASM_ARCH_GPIO_H 9*1f8f7730SSimon Glass 10*1f8f7730SSimon Glass struct rockchip_gpio_regs { 11*1f8f7730SSimon Glass u32 swport_dr; 12*1f8f7730SSimon Glass u32 swport_ddr; 13*1f8f7730SSimon Glass u32 reserved0[(0x30 - 0x08) / 4]; 14*1f8f7730SSimon Glass u32 inten; 15*1f8f7730SSimon Glass u32 intmask; 16*1f8f7730SSimon Glass u32 inttype_level; 17*1f8f7730SSimon Glass u32 int_polarity; 18*1f8f7730SSimon Glass u32 int_status; 19*1f8f7730SSimon Glass u32 int_rawstatus; 20*1f8f7730SSimon Glass u32 debounce; 21*1f8f7730SSimon Glass u32 porta_eoi; 22*1f8f7730SSimon Glass u32 ext_port; 23*1f8f7730SSimon Glass u32 reserved1[(0x60 - 0x54) / 4]; 24*1f8f7730SSimon Glass u32 ls_sync; 25*1f8f7730SSimon Glass }; 26*1f8f7730SSimon Glass check_member(rockchip_gpio_regs, ls_sync, 0x60); 27*1f8f7730SSimon Glass 28*1f8f7730SSimon Glass #endif 29