xref: /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/gpio.h (revision d1aef94b5af0d0191a8f53dfdd2a1d661a1c54cd)
11f8f7730SSimon Glass /*
21f8f7730SSimon Glass  * (C) Copyright 2015 Google, Inc
31f8f7730SSimon Glass  *
41f8f7730SSimon Glass  * SPDX-License-Identifier:     GPL-2.0+
51f8f7730SSimon Glass  */
61f8f7730SSimon Glass 
71f8f7730SSimon Glass #ifndef _ASM_ARCH_GPIO_H
81f8f7730SSimon Glass #define _ASM_ARCH_GPIO_H
91f8f7730SSimon Glass 
10*d1aef94bSJianqun Xu #ifndef CONFIG_ROCKCHIP_GPIO_V2
111f8f7730SSimon Glass struct rockchip_gpio_regs {
121f8f7730SSimon Glass 	u32 swport_dr;
131f8f7730SSimon Glass 	u32 swport_ddr;
141f8f7730SSimon Glass 	u32 reserved0[(0x30 - 0x08) / 4];
151f8f7730SSimon Glass 	u32 inten;
161f8f7730SSimon Glass 	u32 intmask;
171f8f7730SSimon Glass 	u32 inttype_level;
181f8f7730SSimon Glass 	u32 int_polarity;
191f8f7730SSimon Glass 	u32 int_status;
201f8f7730SSimon Glass 	u32 int_rawstatus;
211f8f7730SSimon Glass 	u32 debounce;
221f8f7730SSimon Glass 	u32 porta_eoi;
231f8f7730SSimon Glass 	u32 ext_port;
241f8f7730SSimon Glass 	u32 reserved1[(0x60 - 0x54) / 4];
251f8f7730SSimon Glass 	u32 ls_sync;
261f8f7730SSimon Glass };
271f8f7730SSimon Glass check_member(rockchip_gpio_regs, ls_sync, 0x60);
28*d1aef94bSJianqun Xu #else
29*d1aef94bSJianqun Xu struct rockchip_gpio_regs {
30*d1aef94bSJianqun Xu 	u32 swport_dr_l;                        /* ADDRESS OFFSET: 0x0000 */
31*d1aef94bSJianqun Xu 	u32 swport_dr_h;                        /* ADDRESS OFFSET: 0x0004 */
32*d1aef94bSJianqun Xu 	u32 swport_ddr_l;                       /* ADDRESS OFFSET: 0x0008 */
33*d1aef94bSJianqun Xu 	u32 swport_ddr_h;                       /* ADDRESS OFFSET: 0x000c */
34*d1aef94bSJianqun Xu 	u32 int_en_l;                           /* ADDRESS OFFSET: 0x0010 */
35*d1aef94bSJianqun Xu 	u32 int_en_h;                           /* ADDRESS OFFSET: 0x0014 */
36*d1aef94bSJianqun Xu 	u32 int_mask_l;                         /* ADDRESS OFFSET: 0x0018 */
37*d1aef94bSJianqun Xu 	u32 int_mask_h;                         /* ADDRESS OFFSET: 0x001c */
38*d1aef94bSJianqun Xu 	u32 int_type_l;                         /* ADDRESS OFFSET: 0x0020 */
39*d1aef94bSJianqun Xu 	u32 int_type_h;                         /* ADDRESS OFFSET: 0x0024 */
40*d1aef94bSJianqun Xu 	u32 int_polarity_l;                     /* ADDRESS OFFSET: 0x0028 */
41*d1aef94bSJianqun Xu 	u32 int_polarity_h;                     /* ADDRESS OFFSET: 0x002c */
42*d1aef94bSJianqun Xu 	u32 int_bothedge_l;                     /* ADDRESS OFFSET: 0x0030 */
43*d1aef94bSJianqun Xu 	u32 int_bothedge_h;                     /* ADDRESS OFFSET: 0x0034 */
44*d1aef94bSJianqun Xu 	u32 debounce_l;                         /* ADDRESS OFFSET: 0x0038 */
45*d1aef94bSJianqun Xu 	u32 debounce_h;                         /* ADDRESS OFFSET: 0x003c */
46*d1aef94bSJianqun Xu 	u32 dbclk_div_en_l;                     /* ADDRESS OFFSET: 0x0040 */
47*d1aef94bSJianqun Xu 	u32 dbclk_div_en_h;                     /* ADDRESS OFFSET: 0x0044 */
48*d1aef94bSJianqun Xu 	u32 dbclk_div_con;                      /* ADDRESS OFFSET: 0x0048 */
49*d1aef94bSJianqun Xu 	u32 reserved004c;                       /* ADDRESS OFFSET: 0x004c */
50*d1aef94bSJianqun Xu 	u32 int_status;                         /* ADDRESS OFFSET: 0x0050 */
51*d1aef94bSJianqun Xu 	u32 reserved0054;                       /* ADDRESS OFFSET: 0x0054 */
52*d1aef94bSJianqun Xu 	u32 int_rawstatus;                      /* ADDRESS OFFSET: 0x0058 */
53*d1aef94bSJianqun Xu 	u32 reserved005c;                       /* ADDRESS OFFSET: 0x005c */
54*d1aef94bSJianqun Xu 	u32 port_eoi_l;                         /* ADDRESS OFFSET: 0x0060 */
55*d1aef94bSJianqun Xu 	u32 port_eoi_h;                         /* ADDRESS OFFSET: 0x0064 */
56*d1aef94bSJianqun Xu 	u32 reserved0068[2];                    /* ADDRESS OFFSET: 0x0068 */
57*d1aef94bSJianqun Xu 	u32 ext_port;                           /* ADDRESS OFFSET: 0x0070 */
58*d1aef94bSJianqun Xu 	u32 reserved0074;                       /* ADDRESS OFFSET: 0x0074 */
59*d1aef94bSJianqun Xu 	u32 ver_id;                             /* ADDRESS OFFSET: 0x0078 */
60*d1aef94bSJianqun Xu };
61*d1aef94bSJianqun Xu check_member(rockchip_gpio_regs, ver_id, 0x0078);
62*d1aef94bSJianqun Xu #endif
631f8f7730SSimon Glass 
641f8f7730SSimon Glass #endif
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