1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4 * Author: Joseph Chen <chenjh@rock-chips.com> 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RK3528_H 8 #define _ASM_ARCH_CRU_RK3528_H 9 10 #define MHz 1000000 11 #define KHz 1000 12 #define OSC_HZ (24 * MHz) 13 14 #define APLL_HZ (408 * MHz) 15 #define GPLL_HZ (1188 * MHz) 16 #define CPLL_HZ (996 * MHz) 17 #define PPLL_HZ (1000 * MHz) 18 19 /* RK3528 pll id */ 20 enum rk3528_pll_id { 21 APLL, 22 CPLL, 23 GPLL, 24 PPLL, 25 DPLL, 26 PLL_COUNT, 27 }; 28 29 struct rk3528_clk_info { 30 unsigned long id; 31 char *name; 32 }; 33 34 struct rk3528_clk_priv { 35 struct rk3528_cru *cru; 36 struct rk3528_sysgrf *grf; 37 ulong ppll_hz; 38 ulong gpll_hz; 39 ulong cpll_hz; 40 ulong armclk_hz; 41 ulong armclk_enter_hz; 42 ulong armclk_init_hz; 43 bool sync_kernel; 44 bool set_armclk_rate; 45 }; 46 47 struct rk3528_pll { 48 unsigned int con0; 49 unsigned int con1; 50 unsigned int con2; 51 unsigned int con3; 52 unsigned int con4; 53 unsigned int reserved0[3]; 54 }; 55 56 struct rk3528_cru { 57 uint32_t apll_con[5]; 58 uint32_t reserved0014[3]; 59 uint32_t cpll_con[5]; 60 uint32_t reserved0034[11]; 61 uint32_t gpll_con[5]; 62 uint32_t reserved0074[51+32]; 63 uint32_t reserved01c0[48]; 64 uint32_t mode_con[1]; 65 uint32_t reserved0284[31]; 66 uint32_t clksel_con[91]; 67 uint32_t reserved046c[229]; 68 uint32_t gate_con[46]; 69 uint32_t reserved08b8[82]; 70 uint32_t softrst_con[47]; 71 uint32_t reserved0abc[81]; 72 uint32_t glb_cnt_th; 73 uint32_t glb_rst_st; 74 uint32_t glb_srst_fst; 75 uint32_t glb_srst_snd; 76 uint32_t glb_rst_con; 77 uint32_t reserved0c14[6]; 78 uint32_t corewfi_con; 79 uint32_t reserved0c30[15604]; 80 81 /* pmucru */ 82 uint32_t reserved10000[192]; 83 uint32_t pmuclksel_con[3]; 84 uint32_t reserved1030c[317]; 85 uint32_t pmugate_con[3]; 86 uint32_t reserved1080c[125]; 87 uint32_t pmusoftrst_con[3]; 88 uint32_t reserved10a08[7550+8191]; 89 90 /* pciecru */ 91 uint32_t reserved20000[32]; 92 uint32_t ppll_con[5]; 93 uint32_t reserved20094[155]; 94 uint32_t pcieclksel_con[2]; 95 uint32_t reserved20308[318]; 96 uint32_t pciegate_con; 97 }; 98 check_member(rk3528_cru, pciegate_con, 0x20800); 99 100 struct rk3528_grf_clk_priv { 101 struct rk3528_grf *grf; 102 }; 103 104 struct pll_rate_table { 105 unsigned long rate; 106 unsigned int fbdiv; 107 unsigned int postdiv1; 108 unsigned int refdiv; 109 unsigned int postdiv2; 110 unsigned int dsmpd; 111 unsigned int frac; 112 }; 113 114 #define RK3528_PMU_CRU_BASE 0x10000 115 #define RK3528_PCIE_CRU_BASE 0x20000 116 #define RK3528_DDRPHY_CRU_BASE 0x28000 117 #define RK3528_PLL_CON(x) ((x) * 0x4) 118 #define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE) 119 #define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE) 120 #define RK3528_MODE_CON 0x280 121 #define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300) 122 #define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE) 123 #define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE) 124 #define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE) 125 126 #define RK3528_DIV_ACLK_M_CORE_MASK 0x1f 127 #define RK3528_DIV_ACLK_M_CORE_SHIFT 11 128 #define RK3528_DIV_PCLK_DBG_MASK 0x1f 129 #define RK3528_DIV_PCLK_DBG_SHIFT 1 130 131 enum { 132 /* pmu cru */ 133 PMUCRU_CLKSEL_CON0_CLK_I2C2_SEL_SHIFT = 0, 134 PMUCRU_CLKSEL_CON0_CLK_I2C2_SEL_MASK = 0x3 << PMUCRU_CLKSEL_CON0_CLK_I2C2_SEL_SHIFT, 135 136 /* pcie cru */ 137 PCEICRU_CLKSEL_CON01_CLK_MATRIX_50M_SRC_DIV_SHIFT = 7, 138 PCEICRU_CLKSEL_CON01_CLK_MATRIX_50M_SRC_DIV_MASK = 0x1f << PCEICRU_CLKSEL_CON01_CLK_MATRIX_50M_SRC_DIV_SHIFT, 139 PCEICRU_CLKSEL_CON01_CLK_MATRIX_100M_SRC_DIV_SHIFT = 11, 140 PCEICRU_CLKSEL_CON01_CLK_MATRIX_100M_SRC_DIV_MASK = 0x1f << PCEICRU_CLKSEL_CON01_CLK_MATRIX_100M_SRC_DIV_SHIFT, 141 142 143 CRU_CLKSEL_CON60_CLK_MATRIX_25M_SRC_DIV_SHIFT = 2, 144 CRU_CLKSEL_CON60_CLK_MATRIX_25M_SRC_DIV_MASK = 0xff << CRU_CLKSEL_CON60_CLK_MATRIX_25M_SRC_DIV_SHIFT, 145 CRU_CLKSEL_CON60_CLK_MATRIX_125M_SRC_DIV_SHIFT = 10, 146 CRU_CLKSEL_CON60_CLK_MATRIX_125M_SRC_DIV_MASK = 0x1f << CRU_CLKSEL_CON60_CLK_MATRIX_125M_SRC_DIV_SHIFT, 147 148 149 CRU_CLKSEL_CON63_CLK_I2C3_SEL_SHIFT = 12, 150 CRU_CLKSEL_CON63_CLK_I2C3_SEL_MASK = 0x3 << CRU_CLKSEL_CON63_CLK_I2C3_SEL_SHIFT, 151 152 CRU_CLKSEL_CON63_CLK_I2C5_SEL_SHIFT = 14, 153 CRU_CLKSEL_CON63_CLK_I2C5_SEL_MASK = 0x3 << CRU_CLKSEL_CON63_CLK_I2C5_SEL_SHIFT, 154 CRU_CLKSEL_CON64_CLK_I2C6_SEL_SHIFT = 0, 155 CRU_CLKSEL_CON64_CLK_I2C6_SEL_MASK = 0x3 << CRU_CLKSEL_CON64_CLK_I2C6_SEL_SHIFT, 156 CRU_CLKSEL_CON79_CLK_I2C1_SEL_SHIFT = 9, 157 CRU_CLKSEL_CON79_CLK_I2C1_SEL_MASK = 0x3 << CRU_CLKSEL_CON79_CLK_I2C1_SEL_SHIFT, 158 CRU_CLKSEL_CON79_CLK_I2C0_SEL_SHIFT = 11, 159 CRU_CLKSEL_CON79_CLK_I2C0_SEL_MASK = 0x3 << CRU_CLKSEL_CON79_CLK_I2C0_SEL_SHIFT, 160 CRU_CLKSEL_CON85_CLK_I2C4_SEL_SHIFT = 13, 161 CRU_CLKSEL_CON85_CLK_I2C4_SEL_MASK = 0x3 << CRU_CLKSEL_CON85_CLK_I2C4_SEL_SHIFT, 162 CRU_CLKSEL_CON86_CLK_I2C7_SEL_SHIFT = 0, 163 CRU_CLKSEL_CON86_CLK_I2C7_SEL_MASK = 0x3 << CRU_CLKSEL_CON86_CLK_I2C7_SEL_SHIFT, 164 165 CLK_I2C3_SEL_CLK_MATRIX_200M_SRC = 0U, 166 CLK_I2C3_SEL_CLK_MATRIX_100M_SRC = 1U, 167 CLK_I2C3_SEL_CLK_MATRIX_50M_SRC = 2U, 168 CLK_I2C3_SEL_XIN_OSC0_FUNC = 3U, 169 170 171 CRU_CLKSEL_CON63_CLK_SPI1_SEL_SHIFT = 10, 172 CRU_CLKSEL_CON63_CLK_SPI1_SEL_MASK = 0x3 << CRU_CLKSEL_CON63_CLK_SPI1_SEL_SHIFT, 173 CRU_CLKSEL_CON79_CLK_SPI0_SEL_SHIFT = 13, 174 CRU_CLKSEL_CON79_CLK_SPI0_SEL_MASK = 0x3 << CRU_CLKSEL_CON79_CLK_SPI0_SEL_SHIFT, 175 CLK_SPI1_SEL_CLK_MATRIX_200M_SRC = 0U, 176 CLK_SPI1_SEL_CLK_MATRIX_100M_SRC = 1U, 177 CLK_SPI1_SEL_CLK_MATRIX_50M_SRC = 2U, 178 CLK_SPI1_SEL_XIN_OSC0_FUNC = 3U, 179 180 181 CRU_CLKSEL_CON44_CLK_PWM0_SEL_SHIFT = 6, 182 CRU_CLKSEL_CON44_CLK_PWM0_SEL_MASK = 0x3 << CRU_CLKSEL_CON44_CLK_PWM0_SEL_SHIFT, 183 CRU_CLKSEL_CON44_CLK_PWM1_SEL_SHIFT = 8, 184 CRU_CLKSEL_CON44_CLK_PWM1_SEL_MASK = 0x3 << CRU_CLKSEL_CON44_CLK_PWM1_SEL_SHIFT, 185 CLK_PWM0_SEL_CLK_MATRIX_100M_SRC = 0U, 186 CLK_PWM0_SEL_CLK_MATRIX_50M_SRC = 1U, 187 CLK_PWM0_SEL_XIN_OSC0_FUNC = 2U, 188 CLK_PWM1_SEL_CLK_MATRIX_100M_SRC = 0U, 189 CLK_PWM1_SEL_CLK_MATRIX_50M_SRC = 1U, 190 CLK_PWM1_SEL_XIN_OSC0_FUNC = 2U, 191 192 193 CRU_CLKSEL_CON43_CLK_CORE_CRYPTO_SEL_SHIFT = 14, 194 CRU_CLKSEL_CON43_CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CRU_CLKSEL_CON43_CLK_CORE_CRYPTO_SEL_SHIFT, 195 CRU_CLKSEL_CON44_CLK_PKA_CRYPTO_SEL_SHIFT = 0, 196 CRU_CLKSEL_CON44_CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CRU_CLKSEL_CON44_CLK_PKA_CRYPTO_SEL_SHIFT, 197 CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U, 198 CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U, 199 CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U, 200 CLK_CORE_CRYPTO_SEL_XIN_OSC0_FUNC = 3U, 201 CLK_PKA_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U, 202 CLK_PKA_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U, 203 CLK_PKA_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U, 204 CLK_PKA_CRYPTO_SEL_XIN_OSC0_FUNC = 3U, 205 206 207 CRU_CLKSEL_CON61_SCLK_SFC_DIV_SHIFT = 6, 208 CRU_CLKSEL_CON61_SCLK_SFC_DIV_MASK = 0x3F << CRU_CLKSEL_CON61_SCLK_SFC_DIV_SHIFT, 209 CRU_CLKSEL_CON61_SCLK_SFC_SEL_SHIFT = 12, 210 CRU_CLKSEL_CON61_SCLK_SFC_SEL_MASK = 0x3 << CRU_CLKSEL_CON61_SCLK_SFC_SEL_SHIFT, 211 SCLK_SFC_SEL_CLK_GPLL_MUX = 0U, 212 SCLK_SFC_SEL_CLK_CPLL_MUX = 1U, 213 SCLK_SFC_SEL_XIN_OSC0_FUNC = 2U, 214 215 CRU_CLKSEL_CON74_CLK_SARADC_DIV_SHIFT = 0, 216 CRU_CLKSEL_CON74_CLK_SARADC_DIV_MASK = 0x7 << CRU_CLKSEL_CON74_CLK_SARADC_DIV_SHIFT, 217 218 CRU_CLKSEL_CON74_CLK_TSADC_DIV_SHIFT = 3, 219 CRU_CLKSEL_CON74_CLK_TSADC_DIV_MASK = 0x1F << CRU_CLKSEL_CON74_CLK_TSADC_DIV_SHIFT, 220 CRU_CLKSEL_CON74_CLK_TSADC_TSEN_DIV_SHIFT = 8, 221 CRU_CLKSEL_CON74_CLK_TSADC_TSEN_DIV_MASK = 0x1F << CRU_CLKSEL_CON74_CLK_TSADC_TSEN_DIV_SHIFT, 222 223 CRU_CLKSEL_CON62_CCLK_SRC_EMMC_DIV_SHIFT = 0, 224 CRU_CLKSEL_CON62_CCLK_SRC_EMMC_DIV_MASK = 0x3F << CRU_CLKSEL_CON62_CCLK_SRC_EMMC_DIV_SHIFT, 225 CRU_CLKSEL_CON62_CCLK_SRC_EMMC_SEL_SHIFT = 6, 226 CRU_CLKSEL_CON62_CCLK_SRC_EMMC_SEL_MASK = 0x3 << CRU_CLKSEL_CON62_CCLK_SRC_EMMC_SEL_SHIFT, 227 CRU_CLKSEL_CON62_BCLK_EMMC_SEL_SHIFT = 8, 228 CRU_CLKSEL_CON62_BCLK_EMMC_SEL_MASK = 0x3 << CRU_CLKSEL_CON62_BCLK_EMMC_SEL_SHIFT, 229 CRU_CLKSEL_CON85_CCLK_SRC_SDMMC0_DIV_SHIFT = 0, 230 CRU_CLKSEL_CON85_CCLK_SRC_SDMMC0_DIV_MASK = 0x3F << CRU_CLKSEL_CON85_CCLK_SRC_SDMMC0_DIV_SHIFT, 231 CRU_CLKSEL_CON85_CCLK_SRC_SDMMC0_SEL_SHIFT = 6, 232 CRU_CLKSEL_CON85_CCLK_SRC_SDMMC0_SEL_MASK = 0x3 << CRU_CLKSEL_CON85_CCLK_SRC_SDMMC0_SEL_SHIFT, 233 CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX = 0U, 234 CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX = 1U, 235 CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC = 2U, 236 BCLK_EMMC_SEL_CLK_MATRIX_200M_SRC = 0U, 237 BCLK_EMMC_SEL_CLK_MATRIX_100M_SRC = 1U, 238 BCLK_EMMC_SEL_CLK_MATRIX_50M_SRC = 2U, 239 BCLK_EMMC_SEL_XIN_OSC0_FUNC = 3U, 240 CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX = 0U, 241 CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX = 1U, 242 CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC = 2U, 243 244 CRU_CLKSEL_CON32_DCLK_VOP_SRC0_SEL_SHIFT = 10, 245 CRU_CLKSEL_CON32_DCLK_VOP_SRC0_SEL_MASK = 0x1 << CRU_CLKSEL_CON32_DCLK_VOP_SRC0_SEL_SHIFT, 246 CRU_CLKSEL_CON32_DCLK_VOP_SRC0_DIV_SHIFT = 2, 247 CRU_CLKSEL_CON32_DCLK_VOP_SRC0_DIV_MASK = 0xFF << CRU_CLKSEL_CON32_DCLK_VOP_SRC0_DIV_SHIFT, 248 249 CRU_CLKSEL_CON33_DCLK_VOP_SRC1_SEL_SHIFT = 8, 250 CRU_CLKSEL_CON33_DCLK_VOP_SRC1_SEL_MASK = 0x1 << CRU_CLKSEL_CON33_DCLK_VOP_SRC1_SEL_SHIFT, 251 CRU_CLKSEL_CON33_DCLK_VOP_SRC1_DIV_SHIFT = 0, 252 CRU_CLKSEL_CON33_DCLK_VOP_SRC1_DIV_MASK = 0xFF << CRU_CLKSEL_CON33_DCLK_VOP_SRC1_DIV_SHIFT, 253 254 CRU_CLKSEL_CON83_ACLK_VOP_ROOT_DIV_SHIFT = 12, 255 CRU_CLKSEL_CON83_ACLK_VOP_ROOT_DIV_MASK = 0x7 << CRU_CLKSEL_CON83_ACLK_VOP_ROOT_DIV_SHIFT, 256 CRU_CLKSEL_CON83_ACLK_VOP_ROOT_SEL_SHIFT = 15, 257 CRU_CLKSEL_CON83_ACLK_VOP_ROOT_SEL_MASK = 0x1 << CRU_CLKSEL_CON83_ACLK_VOP_ROOT_SEL_SHIFT, 258 CRU_CLKSEL_CON84_DCLK_VOP0_SEL_SHIFT = 0, 259 CRU_CLKSEL_CON84_DCLK_VOP0_SEL_MASK = 0x1 << CRU_CLKSEL_CON84_DCLK_VOP0_SEL_SHIFT, 260 CLK_TESTOUT_TOP_SEL_ACLK_VOP_ROOT = 6U, 261 262 DCLK_VOP_SRC_SEL_CLK_GPLL_MUX = 0U, 263 DCLK_VOP_SRC_SEL_CLK_CPLL_MUX = 1U, 264 265 ACLK_VOP_ROOT_SEL_CLK_GPLL_MUX = 0U, 266 ACLK_VOP_ROOT_SEL_CLK_CPLL_MUX = 1U, 267 DCLK_VOP0_SEL_DCLK_VOP_SRC0 = 0U, 268 DCLK_VOP0_SEL_CLK_HDMIPHY_PIXEL_IO = 1U, 269 270 271 CRU_CLKSEL_CON04_CLK_UART0_SRC_DIV_SHIFT = 5, 272 CRU_CLKSEL_CON04_CLK_UART0_SRC_DIV_MASK = 0x1F << CRU_CLKSEL_CON04_CLK_UART0_SRC_DIV_SHIFT, 273 CRU_CLKSEL_CON05_CLK_UART0_FRAC_DIV_SHIFT = 0, 274 CRU_CLKSEL_CON05_CLK_UART0_FRAC_DIV_MASK = 0xFFFFFFFF << CRU_CLKSEL_CON05_CLK_UART0_FRAC_DIV_SHIFT, 275 CRU_CLKSEL_CON06_SCLK_UART0_SRC_SEL_SHIFT = 0, 276 CRU_CLKSEL_CON06_SCLK_UART0_SRC_SEL_MASK = 0x3 << CRU_CLKSEL_CON06_SCLK_UART0_SRC_SEL_SHIFT, 277 CRU_CLKSEL_CON06_CLK_UART1_SRC_DIV_SHIFT = 2, 278 CRU_CLKSEL_CON06_CLK_UART1_SRC_DIV_MASK = 0x1F << CRU_CLKSEL_CON06_CLK_UART1_SRC_DIV_SHIFT, 279 CRU_CLKSEL_CON07_CLK_UART1_FRAC_DIV_SHIFT = 0, 280 CRU_CLKSEL_CON07_CLK_UART1_FRAC_DIV_MASK = 0xFFFFFFFF << CRU_CLKSEL_CON07_CLK_UART1_FRAC_DIV_SHIFT, 281 CRU_CLKSEL_CON08_SCLK_UART1_SRC_SEL_SHIFT = 0, 282 CRU_CLKSEL_CON08_SCLK_UART1_SRC_SEL_MASK = 0x3 << CRU_CLKSEL_CON08_SCLK_UART1_SRC_SEL_SHIFT, 283 CRU_CLKSEL_CON08_CLK_UART2_SRC_DIV_SHIFT = 2, 284 CRU_CLKSEL_CON08_CLK_UART2_SRC_DIV_MASK = 0x1F << CRU_CLKSEL_CON08_CLK_UART2_SRC_DIV_SHIFT, 285 CRU_CLKSEL_CON09_CLK_UART2_FRAC_DIV_SHIFT = 0, 286 CRU_CLKSEL_CON09_CLK_UART2_FRAC_DIV_MASK = 0xFFFFFFFF << CRU_CLKSEL_CON09_CLK_UART2_FRAC_DIV_SHIFT, 287 CRU_CLKSEL_CON10_SCLK_UART2_SRC_SEL_SHIFT = 0, 288 CRU_CLKSEL_CON10_SCLK_UART2_SRC_SEL_MASK = 0x3 << CRU_CLKSEL_CON10_SCLK_UART2_SRC_SEL_SHIFT, 289 CRU_CLKSEL_CON10_CLK_UART3_SRC_DIV_SHIFT = 2, 290 CRU_CLKSEL_CON10_CLK_UART3_SRC_DIV_MASK = 0x1F << CRU_CLKSEL_CON10_CLK_UART3_SRC_DIV_SHIFT, 291 CRU_CLKSEL_CON11_CLK_UART3_FRAC_DIV_SHIFT = 0, 292 CRU_CLKSEL_CON11_CLK_UART3_FRAC_DIV_MASK = 0xFFFFFFFF << CRU_CLKSEL_CON11_CLK_UART3_FRAC_DIV_SHIFT, 293 CRU_CLKSEL_CON12_SCLK_UART3_SRC_SEL_SHIFT = 0, 294 CRU_CLKSEL_CON12_SCLK_UART3_SRC_SEL_MASK = 0x3 << CRU_CLKSEL_CON12_SCLK_UART3_SRC_SEL_SHIFT, 295 CRU_CLKSEL_CON12_CLK_UART4_SRC_DIV_SHIFT = 2, 296 CRU_CLKSEL_CON12_CLK_UART4_SRC_DIV_MASK = 0x1F << CRU_CLKSEL_CON12_CLK_UART4_SRC_DIV_SHIFT, 297 CRU_CLKSEL_CON13_CLK_UART4_FRAC_DIV_SHIFT = 0, 298 CRU_CLKSEL_CON13_CLK_UART4_FRAC_DIV_MASK = 0xFFFFFFFF << CRU_CLKSEL_CON13_CLK_UART4_FRAC_DIV_SHIFT, 299 CRU_CLKSEL_CON14_SCLK_UART4_SRC_SEL_SHIFT = 0, 300 CRU_CLKSEL_CON14_SCLK_UART4_SRC_SEL_MASK = 0x3 << CRU_CLKSEL_CON14_SCLK_UART4_SRC_SEL_SHIFT, 301 CRU_CLKSEL_CON14_CLK_UART5_SRC_DIV_SHIFT = 2, 302 CRU_CLKSEL_CON14_CLK_UART5_SRC_DIV_MASK = 0x1F << CRU_CLKSEL_CON14_CLK_UART5_SRC_DIV_SHIFT, 303 CRU_CLKSEL_CON15_CLK_UART5_FRAC_DIV_SHIFT = 0, 304 CRU_CLKSEL_CON15_CLK_UART5_FRAC_DIV_MASK = 0xFFFFFFFF << CRU_CLKSEL_CON15_CLK_UART5_FRAC_DIV_SHIFT, 305 CRU_CLKSEL_CON16_SCLK_UART5_SRC_SEL_SHIFT = 0, 306 CRU_CLKSEL_CON16_SCLK_UART5_SRC_SEL_MASK = 0x3 << CRU_CLKSEL_CON16_SCLK_UART5_SRC_SEL_SHIFT, 307 CRU_CLKSEL_CON16_CLK_UART6_SRC_DIV_SHIFT = 2, 308 CRU_CLKSEL_CON16_CLK_UART6_SRC_DIV_MASK = 0x1F << CRU_CLKSEL_CON16_CLK_UART6_SRC_DIV_SHIFT, 309 CRU_CLKSEL_CON17_CLK_UART6_FRAC_DIV_SHIFT = 0, 310 CRU_CLKSEL_CON17_CLK_UART6_FRAC_DIV_MASK = 0xFFFFFFFF << CRU_CLKSEL_CON17_CLK_UART6_FRAC_DIV_SHIFT, 311 CRU_CLKSEL_CON18_SCLK_UART6_SRC_SEL_SHIFT = 0, 312 CRU_CLKSEL_CON18_SCLK_UART6_SRC_SEL_MASK = 0x3 << CRU_CLKSEL_CON18_SCLK_UART6_SRC_SEL_SHIFT, 313 CRU_CLKSEL_CON18_CLK_UART7_SRC_DIV_SHIFT = 2, 314 CRU_CLKSEL_CON18_CLK_UART7_SRC_DIV_MASK = 0x1F << CRU_CLKSEL_CON18_CLK_UART7_SRC_DIV_SHIFT, 315 CRU_CLKSEL_CON19_CLK_UART7_FRAC_DIV_SHIFT = 0, 316 CRU_CLKSEL_CON19_CLK_UART7_FRAC_DIV_MASK = 0xFFFFFFFF << CRU_CLKSEL_CON19_CLK_UART7_FRAC_DIV_SHIFT, 317 CRU_CLKSEL_CON20_SCLK_UART7_SRC_SEL_SHIFT = 0, 318 CRU_CLKSEL_CON20_SCLK_UART7_SRC_SEL_MASK = 0x3 << CRU_CLKSEL_CON20_SCLK_UART7_SRC_SEL_SHIFT, 319 SCLK_UART0_SRC_SEL_CLK_UART0_SRC = 0U, 320 SCLK_UART0_SRC_SEL_CLK_UART0_FRAC = 1U, 321 SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC = 2U, 322 323 324 CRU_CLKSEL_CON60_CLK_GMAC1_VPU_25M_DIV_SHIFT = 2, 325 CRU_CLKSEL_CON60_CLK_GMAC1_VPU_25M_DIV_MASK = 0xFF << CRU_CLKSEL_CON60_CLK_GMAC1_VPU_25M_DIV_SHIFT, 326 CRU_CLKSEL_CON66_CLK_GMAC1_SRC_VPU_DIV_SHIFT = 0, 327 CRU_CLKSEL_CON66_CLK_GMAC1_SRC_VPU_DIV_MASK = 0x3F << CRU_CLKSEL_CON66_CLK_GMAC1_SRC_VPU_DIV_SHIFT, 328 CRU_CLKSEL_CON84_CLK_GMAC0_SRC_DIV_SHIFT = 3, 329 CRU_CLKSEL_CON84_CLK_GMAC0_SRC_DIV_MASK = 0x3F << CRU_CLKSEL_CON84_CLK_GMAC0_SRC_DIV_SHIFT, 330 331 CRU_CLKSEL_CON43_ACLK_BUS_VOPGL_ROOT_DIV_SHIFT = 0U, 332 CRU_CLKSEL_CON43_ACLK_BUS_VOPGL_ROOT_DIV_MASK = 0x7U << CRU_CLKSEL_CON43_ACLK_BUS_VOPGL_ROOT_DIV_SHIFT, 333 334 CRU_CLKSEL_CON00_CLK_MATRIX_50M_SRC_DIV_SHIFT = 2, 335 CRU_CLKSEL_CON00_CLK_MATRIX_50M_SRC_DIV_MASK = 0x1F << CRU_CLKSEL_CON00_CLK_MATRIX_50M_SRC_DIV_SHIFT, 336 CRU_CLKSEL_CON00_CLK_MATRIX_100M_SRC_DIV_SHIFT = 7, 337 CRU_CLKSEL_CON00_CLK_MATRIX_100M_SRC_DIV_MASK = 0x1F << CRU_CLKSEL_CON00_CLK_MATRIX_100M_SRC_DIV_SHIFT, 338 CRU_CLKSEL_CON01_CLK_MATRIX_150M_SRC_DIV_SHIFT = 0, 339 CRU_CLKSEL_CON01_CLK_MATRIX_150M_SRC_DIV_MASK = 0x1F << CRU_CLKSEL_CON01_CLK_MATRIX_150M_SRC_DIV_SHIFT, 340 CRU_CLKSEL_CON01_CLK_MATRIX_200M_SRC_DIV_SHIFT = 5, 341 CRU_CLKSEL_CON01_CLK_MATRIX_200M_SRC_DIV_MASK = 0x1F << CRU_CLKSEL_CON01_CLK_MATRIX_200M_SRC_DIV_SHIFT, 342 CRU_CLKSEL_CON01_CLK_MATRIX_250M_SRC_DIV_SHIFT = 10, 343 CRU_CLKSEL_CON01_CLK_MATRIX_250M_SRC_DIV_MASK = 0x1F << CRU_CLKSEL_CON01_CLK_MATRIX_250M_SRC_DIV_SHIFT, 344 CRU_CLKSEL_CON01_CLK_MATRIX_250M_SRC_SEL_SHIFT = 15, 345 CRU_CLKSEL_CON01_CLK_MATRIX_250M_SRC_SEL_MASK = 0x1 << CRU_CLKSEL_CON01_CLK_MATRIX_250M_SRC_SEL_SHIFT, 346 CRU_CLKSEL_CON02_CLK_MATRIX_300M_SRC_DIV_SHIFT = 0, 347 CRU_CLKSEL_CON02_CLK_MATRIX_300M_SRC_DIV_MASK = 0x1F << CRU_CLKSEL_CON02_CLK_MATRIX_300M_SRC_DIV_SHIFT, 348 CRU_CLKSEL_CON02_CLK_MATRIX_339M_SRC_DIV_SHIFT = 5, 349 CRU_CLKSEL_CON02_CLK_MATRIX_339M_SRC_DIV_MASK = 0x1F << CRU_CLKSEL_CON02_CLK_MATRIX_339M_SRC_DIV_SHIFT, 350 CRU_CLKSEL_CON02_CLK_MATRIX_400M_SRC_DIV_SHIFT = 10, 351 CRU_CLKSEL_CON02_CLK_MATRIX_400M_SRC_DIV_MASK = 0x1F << CRU_CLKSEL_CON02_CLK_MATRIX_400M_SRC_DIV_SHIFT, 352 CRU_CLKSEL_CON03_CLK_MATRIX_500M_SRC_DIV_SHIFT = 6, 353 CRU_CLKSEL_CON03_CLK_MATRIX_500M_SRC_DIV_MASK = 0x1F << CRU_CLKSEL_CON03_CLK_MATRIX_500M_SRC_DIV_SHIFT, 354 CRU_CLKSEL_CON03_CLK_MATRIX_500M_SRC_SEL_SHIFT = 11, 355 CRU_CLKSEL_CON03_CLK_MATRIX_500M_SRC_SEL_MASK = 0x1 << CRU_CLKSEL_CON03_CLK_MATRIX_500M_SRC_SEL_SHIFT, 356 CRU_CLKSEL_CON04_CLK_MATRIX_600M_SRC_DIV_SHIFT = 0, 357 CRU_CLKSEL_CON04_CLK_MATRIX_600M_SRC_DIV_MASK = 0x1F << CRU_CLKSEL_CON04_CLK_MATRIX_600M_SRC_DIV_SHIFT, 358 CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX = 0U, 359 CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX = 1U, 360 CLK_MATRIX_500M_SRC_SEL_CLK_GPLL_MUX = 0U, 361 CLK_MATRIX_500M_SRC_SEL_CLK_CPLL_MUX = 1U, 362 }; 363 364 #endif 365