1 /* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ASM_ARCH_CRU_RK3328_H_ 8 #define __ASM_ARCH_CRU_RK3328_H_ 9 10 #include <common.h> 11 12 struct rk3328_clk_priv { 13 struct rk3328_cru *cru; 14 ulong rate; 15 ulong cpll_hz; 16 ulong gpll_hz; 17 }; 18 19 struct rk3328_cru { 20 u32 apll_con[5]; 21 u32 reserved1[3]; 22 u32 dpll_con[5]; 23 u32 reserved2[3]; 24 u32 cpll_con[5]; 25 u32 reserved3[3]; 26 u32 gpll_con[5]; 27 u32 reserved4[3]; 28 u32 mode_con; 29 u32 misc; 30 u32 reserved5[2]; 31 u32 glb_cnt_th; 32 u32 glb_rst_st; 33 u32 glb_srst_snd_value; 34 u32 glb_srst_fst_value; 35 u32 npll_con[5]; 36 u32 reserved6[(0x100 - 0xb4) / 4]; 37 u32 clksel_con[53]; 38 u32 reserved7[(0x200 - 0x1d4) / 4]; 39 u32 clkgate_con[29]; 40 u32 reserved8[3]; 41 u32 ssgtbl[32]; 42 u32 softrst_con[12]; 43 u32 reserved9[(0x380 - 0x330) / 4]; 44 u32 sdmmc_con[2]; 45 u32 sdio_con[2]; 46 u32 emmc_con[2]; 47 u32 sdmmc_ext_con[2]; 48 }; 49 check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c); 50 51 /* PX30 pll id */ 52 enum rk3328_pll_id { 53 APLL, 54 DPLL, 55 CPLL, 56 GPLL, 57 NPLL, 58 PLL_COUNT, 59 }; 60 61 struct rk3328_clk_info { 62 unsigned long id; 63 char *name; 64 bool is_cru; 65 }; 66 67 #define MHz 1000 * 1000 68 #define OSC_HZ (24 * MHz) 69 #define APLL_HZ (600 * MHz) 70 #define GPLL_HZ 491520000 71 #define CPLL_HZ (1200 * MHz) 72 #define ACLK_BUS_HZ (150 * MHz) 73 #define ACLK_PERI_HZ (150 * MHz) 74 #define PWM_CLOCK_HZ (74 * MHz) 75 76 #define RK3328_PLL_CON(x) ((x) * 0x4) 77 #define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 78 #define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200) 79 #define RK3328_MODE_CON 0x80 80 81 enum { 82 /* CLKSEL_CON0 */ 83 CLK_BUS_PLL_SEL_CPLL = 0, 84 CLK_BUS_PLL_SEL_GPLL = 1, 85 CLK_BUS_PLL_SEL_SHIFT = 13, 86 CLK_BUS_PLL_SEL_MASK = 3 << CLK_BUS_PLL_SEL_SHIFT, 87 ACLK_BUS_DIV_CON_SHIFT = 8, 88 ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT, 89 CORE_CLK_PLL_SEL_SHIFT = 6, 90 CORE_CLK_PLL_SEL_MASK = 3 << CORE_CLK_PLL_SEL_SHIFT, 91 CORE_CLK_PLL_SEL_APLL = 0, 92 CORE_CLK_PLL_SEL_GPLL, 93 CORE_CLK_PLL_SEL_NPLL = 3, 94 CORE_DIV_CON_SHIFT = 0, 95 CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 96 97 /* CLKSEL_CON1 */ 98 PCLK_BUS_DIV_CON_SHIFT = 12, 99 PCLK_BUS_DIV_CON_MASK = 0x7 << PCLK_BUS_DIV_CON_SHIFT, 100 HCLK_BUS_DIV_CON_SHIFT = 8, 101 HCLK_BUS_DIV_CON_MASK = 0x3 << HCLK_BUS_DIV_CON_SHIFT, 102 CORE_ACLK_DIV_SHIFT = 4, 103 CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT, 104 CORE_DBG_DIV_SHIFT = 0, 105 CORE_DBG_DIV_MASK = 0x0f << CORE_DBG_DIV_SHIFT, 106 107 /* CLKSEL_CON27 */ 108 GMAC2IO_PLL_SEL_SHIFT = 7, 109 GMAC2IO_PLL_SEL_MASK = 1 << GMAC2IO_PLL_SEL_SHIFT, 110 GMAC2IO_PLL_SEL_CPLL = 0, 111 GMAC2IO_PLL_SEL_GPLL = 1, 112 GMAC2IO_CLK_DIV_MASK = 0x1f, 113 GMAC2IO_CLK_DIV_SHIFT = 0, 114 115 /* CLKSEL_CON28 */ 116 CLK_PERI_PLL_SEL_CPLL = 0, 117 CLK_PERI_PLL_SEL_GPLL, 118 CLK_PERI_PLL_SEL_HDMIPHY, 119 CLK_PERI_PLL_SEL_SHIFT = 6, 120 CLK_PERI_PLL_SEL_MASK = 3 << CLK_PERI_PLL_SEL_SHIFT, 121 ACLK_PERI_DIV_CON_SHIFT = 0, 122 ACLK_PERI_DIV_CON_MASK = 0x1f, 123 124 /* CLKSEL_CON29 */ 125 PCLK_PERI_DIV_CON_SHIFT = 4, 126 PCLK_PERI_DIV_CON_MASK = 0x7 << PCLK_PERI_DIV_CON_SHIFT, 127 HCLK_PERI_DIV_CON_SHIFT = 0, 128 HCLK_PERI_DIV_CON_MASK = 3 << HCLK_PERI_DIV_CON_SHIFT, 129 130 /* CLKSEL_CON20 */ 131 CRYPTO_PLL_SEL_SHIFT = 7, 132 CRYPTO_PLL_SEL_MASK = 0x1 << CRYPTO_PLL_SEL_SHIFT, 133 CRYPTO_PLL_SEL_CPLL = 0, 134 CRYPTO_PLL_SEL_GPLL, 135 CRYPTO_DIV_SHIFT = 0, 136 CRYPTO_DIV_MASK = 0x7f << CRYPTO_DIV_SHIFT, 137 138 /* CLKSEL_CON22 */ 139 CLK_TSADC_DIV_CON_SHIFT = 0, 140 CLK_TSADC_DIV_CON_MASK = 0x3ff, 141 142 /* CLKSEL_CON23 */ 143 CLK_SARADC_DIV_CON_SHIFT = 0, 144 CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0), 145 CLK_SARADC_DIV_CON_WIDTH = 10, 146 147 /* CLKSEL_CON24 */ 148 CLK_PWM_PLL_SEL_CPLL = 0, 149 CLK_PWM_PLL_SEL_GPLL, 150 CLK_PWM_PLL_SEL_SHIFT = 15, 151 CLK_PWM_PLL_SEL_MASK = 1 << CLK_PWM_PLL_SEL_SHIFT, 152 CLK_PWM_DIV_CON_SHIFT = 8, 153 CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT, 154 155 CLK_SPI_PLL_SEL_CPLL = 0, 156 CLK_SPI_PLL_SEL_GPLL, 157 CLK_SPI_PLL_SEL_SHIFT = 7, 158 CLK_SPI_PLL_SEL_MASK = 1 << CLK_SPI_PLL_SEL_SHIFT, 159 CLK_SPI_DIV_CON_SHIFT = 0, 160 CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT, 161 162 /* CLKSEL_CON30 */ 163 CLK_SDMMC_PLL_SEL_CPLL = 0, 164 CLK_SDMMC_PLL_SEL_GPLL, 165 CLK_SDMMC_PLL_SEL_24M, 166 CLK_SDMMC_PLL_SEL_USBPHY, 167 CLK_SDMMC_PLL_SHIFT = 8, 168 CLK_SDMMC_PLL_MASK = 0x3 << CLK_SDMMC_PLL_SHIFT, 169 CLK_SDMMC_DIV_CON_SHIFT = 0, 170 CLK_SDMMC_DIV_CON_MASK = 0xff << CLK_SDMMC_DIV_CON_SHIFT, 171 172 /* CLKSEL_CON32 */ 173 CLK_EMMC_PLL_SEL_CPLL = 0, 174 CLK_EMMC_PLL_SEL_GPLL, 175 CLK_EMMC_PLL_SEL_24M, 176 CLK_EMMC_PLL_SEL_USBPHY, 177 CLK_EMMC_PLL_SHIFT = 8, 178 CLK_EMMC_PLL_MASK = 0x3 << CLK_EMMC_PLL_SHIFT, 179 CLK_EMMC_DIV_CON_SHIFT = 0, 180 CLK_EMMC_DIV_CON_MASK = 0xff << CLK_EMMC_DIV_CON_SHIFT, 181 182 /* CLKSEL_CON34 */ 183 CLK_I2C_PLL_SEL_CPLL = 0, 184 CLK_I2C_PLL_SEL_GPLL, 185 CLK_I2C_DIV_CON_MASK = 0x7f, 186 CLK_I2C_PLL_SEL_MASK = 1, 187 CLK_I2C1_PLL_SEL_SHIFT = 15, 188 CLK_I2C1_DIV_CON_SHIFT = 8, 189 CLK_I2C0_PLL_SEL_SHIFT = 7, 190 CLK_I2C0_DIV_CON_SHIFT = 0, 191 192 /* CLKSEL_CON35 */ 193 CLK_I2C3_PLL_SEL_SHIFT = 15, 194 CLK_I2C3_DIV_CON_SHIFT = 8, 195 CLK_I2C2_PLL_SEL_SHIFT = 7, 196 CLK_I2C2_DIV_CON_SHIFT = 0, 197 198 /* CRU_CLK_SEL37_CON */ 199 ACLK_VIO_PLL_SEL_CPLL = 0, 200 ACLK_VIO_PLL_SEL_GPLL = 1, 201 ACLK_VIO_PLL_SEL_HDMIPHY = 2, 202 ACLK_VIO_PLL_SEL_USB480M = 3, 203 ACLK_VIO_PLL_SEL_SHIFT = 6, 204 ACLK_VIO_PLL_SEL_MASK = 3 << ACLK_VIO_PLL_SEL_SHIFT, 205 ACLK_VIO_DIV_CON_SHIFT = 0, 206 ACLK_VIO_DIV_CON_MASK = 0x1f << ACLK_VIO_DIV_CON_SHIFT, 207 HCLK_VIO_DIV_CON_SHIFT = 8, 208 HCLK_VIO_DIV_CON_MASK = 0x1f << HCLK_VIO_DIV_CON_SHIFT, 209 210 /* CRU_CLK_SEL39_CON */ 211 ACLK_VOP_PLL_SEL_CPLL = 0, 212 ACLK_VOP_PLL_SEL_GPLL = 1, 213 ACLK_VOP_PLL_SEL_HDMIPHY = 2, 214 ACLK_VOP_PLL_SEL_USB480M = 3, 215 ACLK_VOP_PLL_SEL_SHIFT = 6, 216 ACLK_VOP_PLL_SEL_MASK = 3 << ACLK_VOP_PLL_SEL_SHIFT, 217 ACLK_VOP_DIV_CON_SHIFT = 0, 218 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 219 220 /* CRU_CLK_SEL40_CON */ 221 DCLK_LCDC_PLL_SEL_GPLL = 0, 222 DCLK_LCDC_PLL_SEL_CPLL = 1, 223 DCLK_LCDC_PLL_SEL_SHIFT = 0, 224 DCLK_LCDC_PLL_SEL_MASK = 1 << DCLK_LCDC_PLL_SEL_SHIFT, 225 DCLK_LCDC_SEL_HDMIPHY = 0, 226 DCLK_LCDC_SEL_PLL = 1, 227 DCLK_LCDC_SEL_SHIFT = 1, 228 DCLK_LCDC_SEL_MASK = 1 << DCLK_LCDC_SEL_SHIFT, 229 DCLK_LCDC_DIV_CON_SHIFT = 8, 230 DCLK_LCDC_DIV_CON_MASK = 0xFf << DCLK_LCDC_DIV_CON_SHIFT, 231 }; 232 233 #endif /* __ASM_ARCH_CRU_RK3328_H_ */ 234