1 /* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ASM_ARCH_CRU_RK3328_H_ 8 #define __ASM_ARCH_CRU_RK3328_H_ 9 10 #include <common.h> 11 12 struct rk3328_clk_priv { 13 struct rk3328_cru *cru; 14 ulong rate; 15 ulong cpll_hz; 16 ulong gpll_hz; 17 ulong armclk_hz; 18 ulong armclk_enter_hz; 19 ulong armclk_init_hz; 20 bool sync_kernel; 21 bool set_armclk_rate; 22 }; 23 24 struct rk3328_cru { 25 u32 apll_con[5]; 26 u32 reserved1[3]; 27 u32 dpll_con[5]; 28 u32 reserved2[3]; 29 u32 cpll_con[5]; 30 u32 reserved3[3]; 31 u32 gpll_con[5]; 32 u32 reserved4[3]; 33 u32 mode_con; 34 u32 misc; 35 u32 reserved5[2]; 36 u32 glb_cnt_th; 37 u32 glb_rst_st; 38 u32 glb_srst_snd_value; 39 u32 glb_srst_fst_value; 40 u32 npll_con[5]; 41 u32 reserved6[(0x100 - 0xb4) / 4]; 42 u32 clksel_con[53]; 43 u32 reserved7[(0x200 - 0x1d4) / 4]; 44 u32 clkgate_con[29]; 45 u32 reserved8[3]; 46 u32 ssgtbl[32]; 47 u32 softrst_con[12]; 48 u32 reserved9[(0x380 - 0x330) / 4]; 49 u32 sdmmc_con[2]; 50 u32 sdio_con[2]; 51 u32 emmc_con[2]; 52 u32 sdmmc_ext_con[2]; 53 }; 54 check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c); 55 56 /* PX30 pll id */ 57 enum rk3328_pll_id { 58 APLL, 59 DPLL, 60 CPLL, 61 GPLL, 62 NPLL, 63 PLL_COUNT, 64 }; 65 66 struct rk3328_clk_info { 67 unsigned long id; 68 char *name; 69 bool is_cru; 70 }; 71 72 #define MHz 1000 * 1000 73 #define OSC_HZ (24 * MHz) 74 #define APLL_HZ (600 * MHz) 75 #define GPLL_HZ 491520000 76 #define CPLL_HZ (1200 * MHz) 77 #define ACLK_BUS_HZ (150 * MHz) 78 #define ACLK_PERI_HZ (150 * MHz) 79 #define PWM_CLOCK_HZ (74 * MHz) 80 81 #define RK3328_PLL_CON(x) ((x) * 0x4) 82 #define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 83 #define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200) 84 #define RK3328_MODE_CON 0x80 85 86 enum { 87 /* CLKSEL_CON0 */ 88 CLK_BUS_PLL_SEL_CPLL = 0, 89 CLK_BUS_PLL_SEL_GPLL = 1, 90 CLK_BUS_PLL_SEL_SHIFT = 13, 91 CLK_BUS_PLL_SEL_MASK = 3 << CLK_BUS_PLL_SEL_SHIFT, 92 ACLK_BUS_DIV_CON_SHIFT = 8, 93 ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT, 94 CORE_CLK_PLL_SEL_SHIFT = 6, 95 CORE_CLK_PLL_SEL_MASK = 3 << CORE_CLK_PLL_SEL_SHIFT, 96 CORE_CLK_PLL_SEL_APLL = 0, 97 CORE_CLK_PLL_SEL_GPLL, 98 CORE_CLK_PLL_SEL_NPLL = 3, 99 CORE_DIV_CON_SHIFT = 0, 100 CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 101 102 /* CLKSEL_CON1 */ 103 PCLK_BUS_DIV_CON_SHIFT = 12, 104 PCLK_BUS_DIV_CON_MASK = 0x7 << PCLK_BUS_DIV_CON_SHIFT, 105 HCLK_BUS_DIV_CON_SHIFT = 8, 106 HCLK_BUS_DIV_CON_MASK = 0x3 << HCLK_BUS_DIV_CON_SHIFT, 107 CORE_ACLK_DIV_SHIFT = 4, 108 CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT, 109 CORE_DBG_DIV_SHIFT = 0, 110 CORE_DBG_DIV_MASK = 0x0f << CORE_DBG_DIV_SHIFT, 111 112 /* CLKSEL_CON27 */ 113 GMAC2IO_PLL_SEL_SHIFT = 7, 114 GMAC2IO_PLL_SEL_MASK = 1 << GMAC2IO_PLL_SEL_SHIFT, 115 GMAC2IO_PLL_SEL_CPLL = 0, 116 GMAC2IO_PLL_SEL_GPLL = 1, 117 GMAC2IO_CLK_DIV_MASK = 0x1f, 118 GMAC2IO_CLK_DIV_SHIFT = 0, 119 120 /* CLKSEL_CON28 */ 121 CLK_PERI_PLL_SEL_CPLL = 0, 122 CLK_PERI_PLL_SEL_GPLL, 123 CLK_PERI_PLL_SEL_HDMIPHY, 124 CLK_PERI_PLL_SEL_SHIFT = 6, 125 CLK_PERI_PLL_SEL_MASK = 3 << CLK_PERI_PLL_SEL_SHIFT, 126 ACLK_PERI_DIV_CON_SHIFT = 0, 127 ACLK_PERI_DIV_CON_MASK = 0x1f, 128 129 /* CLKSEL_CON29 */ 130 PCLK_PERI_DIV_CON_SHIFT = 4, 131 PCLK_PERI_DIV_CON_MASK = 0x7 << PCLK_PERI_DIV_CON_SHIFT, 132 HCLK_PERI_DIV_CON_SHIFT = 0, 133 HCLK_PERI_DIV_CON_MASK = 3 << HCLK_PERI_DIV_CON_SHIFT, 134 135 /* CLKSEL_CON20 */ 136 CRYPTO_PLL_SEL_SHIFT = 7, 137 CRYPTO_PLL_SEL_MASK = 0x1 << CRYPTO_PLL_SEL_SHIFT, 138 CRYPTO_PLL_SEL_CPLL = 0, 139 CRYPTO_PLL_SEL_GPLL, 140 CRYPTO_DIV_SHIFT = 0, 141 CRYPTO_DIV_MASK = 0x7f << CRYPTO_DIV_SHIFT, 142 143 /* CLKSEL_CON22 */ 144 CLK_TSADC_DIV_CON_SHIFT = 0, 145 CLK_TSADC_DIV_CON_MASK = 0x3ff, 146 147 /* CLKSEL_CON23 */ 148 CLK_SARADC_DIV_CON_SHIFT = 0, 149 CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0), 150 CLK_SARADC_DIV_CON_WIDTH = 10, 151 152 /* CLKSEL_CON24 */ 153 CLK_PWM_PLL_SEL_CPLL = 0, 154 CLK_PWM_PLL_SEL_GPLL, 155 CLK_PWM_PLL_SEL_SHIFT = 15, 156 CLK_PWM_PLL_SEL_MASK = 1 << CLK_PWM_PLL_SEL_SHIFT, 157 CLK_PWM_DIV_CON_SHIFT = 8, 158 CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT, 159 160 CLK_SPI_PLL_SEL_CPLL = 0, 161 CLK_SPI_PLL_SEL_GPLL, 162 CLK_SPI_PLL_SEL_SHIFT = 7, 163 CLK_SPI_PLL_SEL_MASK = 1 << CLK_SPI_PLL_SEL_SHIFT, 164 CLK_SPI_DIV_CON_SHIFT = 0, 165 CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT, 166 167 /* CLKSEL_CON30 */ 168 CLK_SDMMC_PLL_SEL_CPLL = 0, 169 CLK_SDMMC_PLL_SEL_GPLL, 170 CLK_SDMMC_PLL_SEL_24M, 171 CLK_SDMMC_PLL_SEL_USBPHY, 172 CLK_SDMMC_PLL_SHIFT = 8, 173 CLK_SDMMC_PLL_MASK = 0x3 << CLK_SDMMC_PLL_SHIFT, 174 CLK_SDMMC_DIV_CON_SHIFT = 0, 175 CLK_SDMMC_DIV_CON_MASK = 0xff << CLK_SDMMC_DIV_CON_SHIFT, 176 177 /* CLKSEL_CON32 */ 178 CLK_EMMC_PLL_SEL_CPLL = 0, 179 CLK_EMMC_PLL_SEL_GPLL, 180 CLK_EMMC_PLL_SEL_24M, 181 CLK_EMMC_PLL_SEL_USBPHY, 182 CLK_EMMC_PLL_SHIFT = 8, 183 CLK_EMMC_PLL_MASK = 0x3 << CLK_EMMC_PLL_SHIFT, 184 CLK_EMMC_DIV_CON_SHIFT = 0, 185 CLK_EMMC_DIV_CON_MASK = 0xff << CLK_EMMC_DIV_CON_SHIFT, 186 187 /* CLKSEL_CON34 */ 188 CLK_I2C_PLL_SEL_CPLL = 0, 189 CLK_I2C_PLL_SEL_GPLL, 190 CLK_I2C_DIV_CON_MASK = 0x7f, 191 CLK_I2C_PLL_SEL_MASK = 1, 192 CLK_I2C1_PLL_SEL_SHIFT = 15, 193 CLK_I2C1_DIV_CON_SHIFT = 8, 194 CLK_I2C0_PLL_SEL_SHIFT = 7, 195 CLK_I2C0_DIV_CON_SHIFT = 0, 196 197 /* CLKSEL_CON35 */ 198 CLK_I2C3_PLL_SEL_SHIFT = 15, 199 CLK_I2C3_DIV_CON_SHIFT = 8, 200 CLK_I2C2_PLL_SEL_SHIFT = 7, 201 CLK_I2C2_DIV_CON_SHIFT = 0, 202 203 /* CRU_CLK_SEL37_CON */ 204 ACLK_VIO_PLL_SEL_CPLL = 0, 205 ACLK_VIO_PLL_SEL_GPLL = 1, 206 ACLK_VIO_PLL_SEL_HDMIPHY = 2, 207 ACLK_VIO_PLL_SEL_USB480M = 3, 208 ACLK_VIO_PLL_SEL_SHIFT = 6, 209 ACLK_VIO_PLL_SEL_MASK = 3 << ACLK_VIO_PLL_SEL_SHIFT, 210 ACLK_VIO_DIV_CON_SHIFT = 0, 211 ACLK_VIO_DIV_CON_MASK = 0x1f << ACLK_VIO_DIV_CON_SHIFT, 212 HCLK_VIO_DIV_CON_SHIFT = 8, 213 HCLK_VIO_DIV_CON_MASK = 0x1f << HCLK_VIO_DIV_CON_SHIFT, 214 215 /* CRU_CLK_SEL39_CON */ 216 ACLK_VOP_PLL_SEL_CPLL = 0, 217 ACLK_VOP_PLL_SEL_GPLL = 1, 218 ACLK_VOP_PLL_SEL_HDMIPHY = 2, 219 ACLK_VOP_PLL_SEL_USB480M = 3, 220 ACLK_VOP_PLL_SEL_SHIFT = 6, 221 ACLK_VOP_PLL_SEL_MASK = 3 << ACLK_VOP_PLL_SEL_SHIFT, 222 ACLK_VOP_DIV_CON_SHIFT = 0, 223 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 224 225 /* CRU_CLK_SEL40_CON */ 226 DCLK_LCDC_PLL_SEL_GPLL = 0, 227 DCLK_LCDC_PLL_SEL_CPLL = 1, 228 DCLK_LCDC_PLL_SEL_SHIFT = 0, 229 DCLK_LCDC_PLL_SEL_MASK = 1 << DCLK_LCDC_PLL_SEL_SHIFT, 230 DCLK_LCDC_SEL_HDMIPHY = 0, 231 DCLK_LCDC_SEL_PLL = 1, 232 DCLK_LCDC_SEL_SHIFT = 1, 233 DCLK_LCDC_SEL_MASK = 1 << DCLK_LCDC_SEL_SHIFT, 234 DCLK_LCDC_DIV_CON_SHIFT = 8, 235 DCLK_LCDC_DIV_CON_MASK = 0xFf << DCLK_LCDC_DIV_CON_SHIFT, 236 }; 237 238 #endif /* __ASM_ARCH_CRU_RK3328_H_ */ 239