1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_CRU_RK3308_H 7 #define _ASM_ARCH_CRU_RK3308_H 8 9 #include <common.h> 10 11 #define MHz 1000000 12 #define OSC_HZ (24 * MHz) 13 14 #define APLL_HZ (816 * MHz) 15 16 #define CORE_ACLK_HZ 408000000 17 #define CORE_DBG_HZ 204000000 18 19 #define BUS_ACLK_HZ 200000000 20 #define BUS_HCLK_HZ 100000000 21 #define BUS_PCLK_HZ 100000000 22 23 #define PERI_ACLK_HZ 200000000 24 #define PERI_HCLK_HZ 100000000 25 #define PERI_PCLK_HZ 100000000 26 27 #define AUDIO_HCLK_HZ 100000000 28 #define AUDIO_PCLK_HZ 100000000 29 30 #define RK3308_PLL_CON(x) ((x) * 0x4) 31 #define RK3308_MODE_CON 0xa0 32 33 /* RK3308 pll id */ 34 enum rk3308_pll_id { 35 APLL, 36 DPLL, 37 VPLL0, 38 VPLL1, 39 PLL_COUNT, 40 }; 41 42 struct rk3308_clk_info { 43 unsigned long id; 44 char *name; 45 }; 46 47 /* Private data for the clock driver - used by rockchip_get_cru() */ 48 struct rk3308_clk_priv { 49 struct rk3308_cru *cru; 50 ulong armclk_hz; 51 ulong dpll_hz; 52 ulong vpll0_hz; 53 ulong vpll1_hz; 54 bool is_assigned; 55 }; 56 57 struct rk3308_cru { 58 struct rk3308_pll { 59 unsigned int con0; 60 unsigned int con1; 61 unsigned int con2; 62 unsigned int con3; 63 unsigned int con4; 64 unsigned int reserved0[3]; 65 } pll[4]; 66 unsigned int reserved1[8]; 67 unsigned int mode; 68 unsigned int misc; 69 unsigned int reserved2[2]; 70 unsigned int glb_cnt_th; 71 unsigned int glb_rst_st; 72 unsigned int glb_srst_fst; 73 unsigned int glb_srst_snd; 74 unsigned int glb_rst_con; 75 unsigned int pll_lock; 76 unsigned int reserved3[6]; 77 unsigned int hwffc_con0; 78 unsigned int reserved4; 79 unsigned int hwffc_th; 80 unsigned int hwffc_intst; 81 unsigned int apll_con0_s; 82 unsigned int apll_con1_s; 83 unsigned int clksel_con0_s; 84 unsigned int reserved5; 85 unsigned int clksel_con[74]; 86 unsigned int reserved6[54]; 87 unsigned int clkgate_con[15]; 88 unsigned int reserved7[(0x380 - 0x338) / 4 - 1]; 89 unsigned int ssgtbl[32]; 90 unsigned int softrst_con[10]; 91 unsigned int reserved8[(0x480 - 0x424) / 4 - 1]; 92 unsigned int sdmmc_con[2]; 93 unsigned int sdio_con[2]; 94 unsigned int emmc_con[2]; 95 }; 96 97 enum { 98 /* PLLCON0*/ 99 PLL_BP_SHIFT = 15, 100 PLL_POSTDIV1_SHIFT = 12, 101 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 102 PLL_FBDIV_SHIFT = 0, 103 PLL_FBDIV_MASK = 0xfff, 104 105 /* PLLCON1 */ 106 PLL_PDSEL_SHIFT = 15, 107 PLL_PD1_SHIFT = 14, 108 PLL_PD_SHIFT = 13, 109 PLL_PD_MASK = 1 << PLL_PD_SHIFT, 110 PLL_DSMPD_SHIFT = 12, 111 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 112 PLL_LOCK_STATUS_SHIFT = 10, 113 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 114 PLL_POSTDIV2_SHIFT = 6, 115 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 116 PLL_REFDIV_SHIFT = 0, 117 PLL_REFDIV_MASK = 0x3f, 118 119 /* PLLCON2 */ 120 PLL_FOUT4PHASEPD_SHIFT = 27, 121 PLL_FOUTVCOPD_SHIFT = 26, 122 PLL_FOUTPOSTDIVPD_SHIFT = 25, 123 PLL_DACPD_SHIFT = 24, 124 PLL_FRAC_DIV = 0xffffff, 125 126 /* CRU_MODE */ 127 PLLMUX_FROM_XIN24M = 0, 128 PLLMUX_FROM_PLL, 129 PLLMUX_FROM_RTC32K, 130 USBPHY480M_MODE_SHIFT = 8, 131 USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT, 132 VPLL1_MODE_SHIFT = 6, 133 VPLL1_MODE_MASK = 3 << VPLL1_MODE_SHIFT, 134 VPLL0_MODE_SHIFT = 4, 135 VPLL0_MODE_MASK = 3 << VPLL0_MODE_SHIFT, 136 DPLL_MODE_SHIFT = 2, 137 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, 138 APLL_MODE_SHIFT = 0, 139 APLL_MODE_MASK = 3 << APLL_MODE_SHIFT, 140 141 /* CRU_CLK_SEL0_CON */ 142 CORE_ACLK_DIV_SHIFT = 12, 143 CORE_ACLK_DIV_MASK = 0x7 << CORE_ACLK_DIV_SHIFT, 144 CORE_DBG_DIV_SHIFT = 8, 145 CORE_DBG_DIV_MASK = 0xf << CORE_DBG_DIV_SHIFT, 146 CORE_CLK_PLL_SEL_SHIFT = 6, 147 CORE_CLK_PLL_SEL_MASK = 0x3 << CORE_CLK_PLL_SEL_SHIFT, 148 CORE_CLK_PLL_SEL_APLL = 0, 149 CORE_CLK_PLL_SEL_VPLL0, 150 CORE_CLK_PLL_SEL_VPLL1, 151 CORE_DIV_CON_SHIFT = 0, 152 CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, 153 154 /* CRU_CLK_SEL5_CON */ 155 BUS_PLL_SEL_SHIFT = 6, 156 BUS_PLL_SEL_MASK = 0x3 << BUS_PLL_SEL_SHIFT, 157 BUS_PLL_SEL_DPLL = 0, 158 BUS_PLL_SEL_VPLL0, 159 BUS_PLL_SEL_VPLL1, 160 BUS_ACLK_DIV_SHIFT = 0, 161 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 162 163 /* CRU_CLK_SEL6_CON */ 164 BUS_PCLK_DIV_SHIFT = 8, 165 BUS_PCLK_DIV_MASK = 0x1f << BUS_PCLK_DIV_SHIFT, 166 BUS_HCLK_DIV_SHIFT = 0, 167 BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT, 168 169 /* CRU_CLK_SEL7_CON */ 170 CRYPTO_APK_SEL_SHIFT = 14, 171 CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT, 172 CRYPTO_PLL_SEL_DPLL = 0, 173 CRYPTO_PLL_SEL_VPLL0, 174 CRYPTO_PLL_SEL_VPLL1 = 0, 175 CRYPTO_APK_DIV_SHIFT = 8, 176 CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT, 177 CRYPTO_PLL_SEL_SHIFT = 6, 178 CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT, 179 CRYPTO_DIV_SHIFT = 0, 180 CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT, 181 182 /* CRU_CLK_SEL8_CON */ 183 DCLK_VOP_SEL_SHIFT = 14, 184 DCLK_VOP_SEL_MASK = 0x3 << DCLK_VOP_SEL_SHIFT, 185 DCLK_VOP_SEL_DIVOUT = 0, 186 DCLK_VOP_SEL_FRACOUT, 187 DCLK_VOP_SEL_24M, 188 DCLK_VOP_PLL_SEL_SHIFT = 10, 189 DCLK_VOP_PLL_SEL_MASK = 0x3 << DCLK_VOP_PLL_SEL_SHIFT, 190 DCLK_VOP_PLL_SEL_DPLL = 0, 191 DCLK_VOP_PLL_SEL_VPLL0, 192 DCLK_VOP_PLL_SEL_VPLL1, 193 DCLK_VOP_DIV_SHIFT = 0, 194 DCLK_VOP_DIV_MASK = 0xff, 195 196 /* CRU_CLK_SEL25_CON */ 197 /* CRU_CLK_SEL26_CON */ 198 /* CRU_CLK_SEL27_CON */ 199 /* CRU_CLK_SEL28_CON */ 200 CLK_I2C_PLL_SEL_SHIFT = 14, 201 CLK_I2C_PLL_SEL_MASK = 0x3 << CLK_I2C_PLL_SEL_SHIFT, 202 CLK_I2C_PLL_SEL_DPLL = 0, 203 CLK_I2C_PLL_SEL_VPLL0, 204 CLK_I2C_PLL_SEL_24M, 205 CLK_I2C_DIV_CON_SHIFT = 0, 206 CLK_I2C_DIV_CON_MASK = 0x7f << CLK_I2C_DIV_CON_SHIFT, 207 208 /* CRU_CLK_SEL29_CON */ 209 CLK_PWM_PLL_SEL_SHIFT = 14, 210 CLK_PWM_PLL_SEL_MASK = 0x3 << CLK_PWM_PLL_SEL_SHIFT, 211 CLK_PWM_PLL_SEL_DPLL = 0, 212 CLK_PWM_PLL_SEL_VPLL0, 213 CLK_PWM_PLL_SEL_24M, 214 CLK_PWM_DIV_CON_SHIFT = 0, 215 CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT, 216 217 /* CRU_CLK_SEL30_CON */ 218 /* CRU_CLK_SEL31_CON */ 219 /* CRU_CLK_SEL32_CON */ 220 CLK_SPI_PLL_SEL_SHIFT = 14, 221 CLK_SPI_PLL_SEL_MASK = 0x3 << CLK_SPI_PLL_SEL_SHIFT, 222 CLK_SPI_PLL_SEL_DPLL = 0, 223 CLK_SPI_PLL_SEL_VPLL0, 224 CLK_SPI_PLL_SEL_24M, 225 CLK_SPI_DIV_CON_SHIFT = 0, 226 CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT, 227 228 /* CRU_CLK_SEL34_CON */ 229 CLK_SARADC_DIV_CON_SHIFT = 0, 230 CLK_SARADC_DIV_CON_MASK = 0x7ff << CLK_SARADC_DIV_CON_SHIFT, 231 232 /* CRU_CLK_SEL36_CON */ 233 PERI_PLL_SEL_SHIFT = 6, 234 PERI_PLL_SEL_MASK = 0x3 << PERI_PLL_SEL_SHIFT, 235 PERI_PLL_DPLL = 0, 236 PERI_PLL_VPLL0, 237 PERI_PLL_VPLL1, 238 PERI_ACLK_DIV_SHIFT = 0, 239 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 240 241 /* CRU_CLK_SEL37_CON */ 242 PERI_PCLK_DIV_SHIFT = 8, 243 PERI_PCLK_DIV_MASK = 0x1f << PERI_PCLK_DIV_SHIFT, 244 PERI_HCLK_DIV_SHIFT = 0, 245 PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT, 246 247 /* CRU_CLKSEL41_CON */ 248 EMMC_CLK_SEL_SHIFT = 15, 249 EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, 250 EMMC_CLK_SEL_EMMC = 0, 251 EMMC_CLK_SEL_EMMC_DIV50, 252 EMMC_PLL_SHIFT = 8, 253 EMMC_PLL_MASK = 0x3 << EMMC_PLL_SHIFT, 254 EMMC_SEL_DPLL = 0, 255 EMMC_SEL_VPLL0, 256 EMMC_SEL_VPLL1, 257 EMMC_SEL_24M, 258 EMMC_DIV_SHIFT = 0, 259 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 260 261 /* CRU_CLK_SEL45_CON */ 262 AUDIO_PCLK_DIV_SHIFT = 8, 263 AUDIO_PCLK_DIV_MASK = 0x1f << AUDIO_PCLK_DIV_SHIFT, 264 AUDIO_PLL_SEL_SHIFT = 6, 265 AUDIO_PLL_SEL_MASK = 0x3 << AUDIO_PLL_SEL_SHIFT, 266 AUDIO_PLL_VPLL0 = 0, 267 AUDIO_PLL_VPLL1, 268 AUDIO_PLL_24M, 269 AUDIO_HCLK_DIV_SHIFT = 0, 270 AUDIO_HCLK_DIV_MASK = 0x1f << AUDIO_HCLK_DIV_SHIFT, 271 }; 272 273 check_member(rk3308_cru, emmc_con[1], 0x494); 274 275 #endif 276