1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_CRU_RK3308_H 7 #define _ASM_ARCH_CRU_RK3308_H 8 9 #include <common.h> 10 11 #define MHz 1000000 12 #define OSC_HZ (24 * MHz) 13 14 #define APLL_HZ (816 * MHz) 15 16 #define CORE_ACLK_HZ 408000000 17 #define CORE_DBG_HZ 204000000 18 19 #define BUS_ACLK_HZ 200000000 20 #define BUS_HCLK_HZ 100000000 21 #define BUS_PCLK_HZ 100000000 22 23 #define PERI_ACLK_HZ 200000000 24 #define PERI_HCLK_HZ 100000000 25 #define PERI_PCLK_HZ 100000000 26 27 #define AUDIO_HCLK_HZ 100000000 28 #define AUDIO_PCLK_HZ 100000000 29 30 #define RK3308_PLL_CON(x) ((x) * 0x4) 31 #define RK3308_MODE_CON 0xa0 32 33 /* RK3308 pll id */ 34 enum rk3308_pll_id { 35 APLL, 36 DPLL, 37 VPLL0, 38 VPLL1, 39 PLL_COUNT, 40 }; 41 42 struct rk3308_clk_info { 43 unsigned long id; 44 char *name; 45 }; 46 47 /* Private data for the clock driver - used by rockchip_get_cru() */ 48 struct rk3308_clk_priv { 49 struct rk3308_cru *cru; 50 ulong armclk_hz;; 51 ulong dpll_hz; 52 ulong vpll0_hz; 53 ulong vpll1_hz; 54 }; 55 56 struct rk3308_cru { 57 struct rk3308_pll { 58 unsigned int con0; 59 unsigned int con1; 60 unsigned int con2; 61 unsigned int con3; 62 unsigned int con4; 63 unsigned int reserved0[3]; 64 } pll[4]; 65 unsigned int reserved1[8]; 66 unsigned int mode; 67 unsigned int misc; 68 unsigned int reserved2[2]; 69 unsigned int glb_cnt_th; 70 unsigned int glb_rst_st; 71 unsigned int glb_srst_fst; 72 unsigned int glb_srst_snd; 73 unsigned int glb_rst_con; 74 unsigned int pll_lock; 75 unsigned int reserved3[6]; 76 unsigned int hwffc_con0; 77 unsigned int reserved4; 78 unsigned int hwffc_th; 79 unsigned int hwffc_intst; 80 unsigned int apll_con0_s; 81 unsigned int apll_con1_s; 82 unsigned int clksel_con0_s; 83 unsigned int reserved5; 84 unsigned int clksel_con[74]; 85 unsigned int reserved6[54]; 86 unsigned int clkgate_con[15]; 87 unsigned int reserved7[(0x380 - 0x338) / 4 - 1]; 88 unsigned int ssgtbl[32]; 89 unsigned int softrst_con[10]; 90 unsigned int reserved8[(0x480 - 0x424) / 4 - 1]; 91 unsigned int sdmmc_con[2]; 92 unsigned int sdio_con[2]; 93 unsigned int emmc_con[2]; 94 }; 95 96 enum { 97 /* PLLCON0*/ 98 PLL_BP_SHIFT = 15, 99 PLL_POSTDIV1_SHIFT = 12, 100 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 101 PLL_FBDIV_SHIFT = 0, 102 PLL_FBDIV_MASK = 0xfff, 103 104 /* PLLCON1 */ 105 PLL_PDSEL_SHIFT = 15, 106 PLL_PD1_SHIFT = 14, 107 PLL_PD_SHIFT = 13, 108 PLL_PD_MASK = 1 << PLL_PD_SHIFT, 109 PLL_DSMPD_SHIFT = 12, 110 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 111 PLL_LOCK_STATUS_SHIFT = 10, 112 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 113 PLL_POSTDIV2_SHIFT = 6, 114 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 115 PLL_REFDIV_SHIFT = 0, 116 PLL_REFDIV_MASK = 0x3f, 117 118 /* PLLCON2 */ 119 PLL_FOUT4PHASEPD_SHIFT = 27, 120 PLL_FOUTVCOPD_SHIFT = 26, 121 PLL_FOUTPOSTDIVPD_SHIFT = 25, 122 PLL_DACPD_SHIFT = 24, 123 PLL_FRAC_DIV = 0xffffff, 124 125 /* CRU_MODE */ 126 PLLMUX_FROM_XIN24M = 0, 127 PLLMUX_FROM_PLL, 128 PLLMUX_FROM_RTC32K, 129 USBPHY480M_MODE_SHIFT = 8, 130 USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT, 131 VPLL1_MODE_SHIFT = 6, 132 VPLL1_MODE_MASK = 3 << VPLL1_MODE_SHIFT, 133 VPLL0_MODE_SHIFT = 4, 134 VPLL0_MODE_MASK = 3 << VPLL0_MODE_SHIFT, 135 DPLL_MODE_SHIFT = 2, 136 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, 137 APLL_MODE_SHIFT = 0, 138 APLL_MODE_MASK = 3 << APLL_MODE_SHIFT, 139 140 /* CRU_CLK_SEL0_CON */ 141 CORE_ACLK_DIV_SHIFT = 12, 142 CORE_ACLK_DIV_MASK = 0x7 << CORE_ACLK_DIV_SHIFT, 143 CORE_DBG_DIV_SHIFT = 8, 144 CORE_DBG_DIV_MASK = 0xf << CORE_DBG_DIV_SHIFT, 145 CORE_CLK_PLL_SEL_SHIFT = 6, 146 CORE_CLK_PLL_SEL_MASK = 0x3 << CORE_CLK_PLL_SEL_SHIFT, 147 CORE_CLK_PLL_SEL_APLL = 0, 148 CORE_CLK_PLL_SEL_VPLL0, 149 CORE_CLK_PLL_SEL_VPLL1, 150 CORE_DIV_CON_SHIFT = 0, 151 CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, 152 153 /* CRU_CLK_SEL5_CON */ 154 BUS_PLL_SEL_SHIFT = 6, 155 BUS_PLL_SEL_MASK = 0x3 << BUS_PLL_SEL_SHIFT, 156 BUS_PLL_SEL_DPLL = 0, 157 BUS_PLL_SEL_VPLL0, 158 BUS_PLL_SEL_VPLL1, 159 BUS_ACLK_DIV_SHIFT = 0, 160 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 161 162 /* CRU_CLK_SEL6_CON */ 163 BUS_PCLK_DIV_SHIFT = 8, 164 BUS_PCLK_DIV_MASK = 0x1f << BUS_PCLK_DIV_SHIFT, 165 BUS_HCLK_DIV_SHIFT = 0, 166 BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT, 167 168 /* CRU_CLK_SEL8_CON */ 169 DCLK_VOP_SEL_SHIFT = 14, 170 DCLK_VOP_SEL_MASK = 0x3 << DCLK_VOP_SEL_SHIFT, 171 DCLK_VOP_SEL_DIVOUT = 0, 172 DCLK_VOP_SEL_FRACOUT, 173 DCLK_VOP_SEL_24M, 174 DCLK_VOP_PLL_SEL_SHIFT = 10, 175 DCLK_VOP_PLL_SEL_MASK = 0x3 << DCLK_VOP_PLL_SEL_SHIFT, 176 DCLK_VOP_PLL_SEL_DPLL = 0, 177 DCLK_VOP_PLL_SEL_VPLL0, 178 DCLK_VOP_PLL_SEL_VPLL1, 179 DCLK_VOP_DIV_SHIFT = 0, 180 DCLK_VOP_DIV_MASK = 0xff, 181 182 /* CRU_CLK_SEL25_CON */ 183 /* CRU_CLK_SEL26_CON */ 184 /* CRU_CLK_SEL27_CON */ 185 /* CRU_CLK_SEL28_CON */ 186 CLK_I2C_PLL_SEL_SHIFT = 14, 187 CLK_I2C_PLL_SEL_MASK = 0x3 << CLK_I2C_PLL_SEL_SHIFT, 188 CLK_I2C_PLL_SEL_DPLL = 0, 189 CLK_I2C_PLL_SEL_VPLL0, 190 CLK_I2C_PLL_SEL_24M, 191 CLK_I2C_DIV_CON_SHIFT = 0, 192 CLK_I2C_DIV_CON_MASK = 0x7f << CLK_I2C_DIV_CON_SHIFT, 193 194 /* CRU_CLK_SEL29_CON */ 195 CLK_PWM_PLL_SEL_SHIFT = 14, 196 CLK_PWM_PLL_SEL_MASK = 0x3 << CLK_PWM_PLL_SEL_SHIFT, 197 CLK_PWM_PLL_SEL_DPLL = 0, 198 CLK_PWM_PLL_SEL_VPLL0, 199 CLK_PWM_PLL_SEL_24M, 200 CLK_PWM_DIV_CON_SHIFT = 0, 201 CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT, 202 203 /* CRU_CLK_SEL30_CON */ 204 /* CRU_CLK_SEL31_CON */ 205 /* CRU_CLK_SEL32_CON */ 206 CLK_SPI_PLL_SEL_SHIFT = 14, 207 CLK_SPI_PLL_SEL_MASK = 0x3 << CLK_SPI_PLL_SEL_SHIFT, 208 CLK_SPI_PLL_SEL_DPLL = 0, 209 CLK_SPI_PLL_SEL_VPLL0, 210 CLK_SPI_PLL_SEL_24M, 211 CLK_SPI_DIV_CON_SHIFT = 0, 212 CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT, 213 214 /* CRU_CLK_SEL34_CON */ 215 CLK_SARADC_DIV_CON_SHIFT = 0, 216 CLK_SARADC_DIV_CON_MASK = 0x7ff << CLK_SARADC_DIV_CON_SHIFT, 217 218 /* CRU_CLK_SEL36_CON */ 219 PERI_PLL_SEL_SHIFT = 6, 220 PERI_PLL_SEL_MASK = 0x3 << PERI_PLL_SEL_SHIFT, 221 PERI_PLL_DPLL = 0, 222 PERI_PLL_VPLL0, 223 PERI_PLL_VPLL1, 224 PERI_ACLK_DIV_SHIFT = 0, 225 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 226 227 /* CRU_CLK_SEL37_CON */ 228 PERI_PCLK_DIV_SHIFT = 8, 229 PERI_PCLK_DIV_MASK = 0x1f << PERI_PCLK_DIV_SHIFT, 230 PERI_HCLK_DIV_SHIFT = 0, 231 PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT, 232 233 /* CRU_CLKSEL41_CON */ 234 EMMC_CLK_SEL_SHIFT = 15, 235 EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, 236 EMMC_CLK_SEL_EMMC = 0, 237 EMMC_CLK_SEL_EMMC_DIV50, 238 EMMC_PLL_SHIFT = 8, 239 EMMC_PLL_MASK = 0x3 << EMMC_PLL_SHIFT, 240 EMMC_SEL_DPLL = 0, 241 EMMC_SEL_VPLL0, 242 EMMC_SEL_VPLL1, 243 EMMC_SEL_24M, 244 EMMC_DIV_SHIFT = 0, 245 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 246 247 /* CRU_CLK_SEL45_CON */ 248 AUDIO_PCLK_DIV_SHIFT = 8, 249 AUDIO_PCLK_DIV_MASK = 0x1f << AUDIO_PCLK_DIV_SHIFT, 250 AUDIO_PLL_SEL_SHIFT = 6, 251 AUDIO_PLL_SEL_MASK = 0x3 << AUDIO_PLL_SEL_SHIFT, 252 AUDIO_PLL_VPLL0 = 0, 253 AUDIO_PLL_VPLL1, 254 AUDIO_PLL_24M, 255 AUDIO_HCLK_DIV_SHIFT = 0, 256 AUDIO_HCLK_DIV_MASK = 0x1f << AUDIO_HCLK_DIV_SHIFT, 257 }; 258 259 check_member(rk3308_cru, emmc_con[1], 0x494); 260 261 #endif 262