1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_CRU_RK3308_H 7 #define _ASM_ARCH_CRU_RK3308_H 8 9 #include <common.h> 10 11 #define MHz 1000000 12 #define OSC_HZ (24 * MHz) 13 14 #define CORE_ACLK_HZ 408000000 15 #define CORE_DBG_HZ 204000000 16 17 #define BUS_ACLK_HZ 200000000 18 #define BUS_HCLK_HZ 100000000 19 #define BUS_PCLK_HZ 100000000 20 21 #define PERI_ACLK_HZ 200000000 22 #define PERI_HCLK_HZ 100000000 23 #define PERI_PCLK_HZ 100000000 24 25 #define AUDIO_HCLK_HZ 100000000 26 #define AUDIO_PCLK_HZ 100000000 27 28 /* RK3308 pll id */ 29 enum rk3308_pll_id { 30 APLL, 31 DPLL, 32 VPLL0, 33 VPLL1, 34 PLL_COUNT, 35 }; 36 37 struct pll_div { 38 u32 refdiv; 39 u32 fbdiv; 40 u32 postdiv1; 41 u32 postdiv2; 42 u32 frac; 43 }; 44 45 /* Private data for the clock driver - used by rockchip_get_cru() */ 46 struct rk3308_clk_priv { 47 struct rk3308_cru *cru; 48 ulong rate; 49 }; 50 51 struct rk3308_cru { 52 struct rk3308_pll { 53 unsigned int con0; 54 unsigned int con1; 55 unsigned int con2; 56 unsigned int con3; 57 unsigned int con4; 58 unsigned int reserved0[3]; 59 } pll[4]; 60 unsigned int reserved1[8]; 61 unsigned int mode; 62 unsigned int misc; 63 unsigned int reserved2[2]; 64 unsigned int glb_cnt_th; 65 unsigned int glb_rst_st; 66 unsigned int glb_srst_fst; 67 unsigned int glb_srst_snd; 68 unsigned int glb_rst_con; 69 unsigned int pll_lock; 70 unsigned int reserved3[6]; 71 unsigned int hwffc_con0; 72 unsigned int reserved4; 73 unsigned int hwffc_th; 74 unsigned int hwffc_intst; 75 unsigned int apll_con0_s; 76 unsigned int apll_con1_s; 77 unsigned int clksel_con0_s; 78 unsigned int reserved5; 79 unsigned int clksel_con[74]; 80 unsigned int reserved6[54]; 81 unsigned int clkgate_con[15]; 82 unsigned int reserved7[(0x380 - 0x338) / 4 - 1]; 83 unsigned int ssgtbl[32]; 84 unsigned int softrst_con[10]; 85 unsigned int reserved8[(0x480 - 0x424) / 4 - 1]; 86 unsigned int sdmmc_con[2]; 87 unsigned int sdio_con[2]; 88 unsigned int emmc_con[2]; 89 }; 90 91 enum { 92 /* PLLCON0*/ 93 PLL_BP_SHIFT = 15, 94 PLL_POSTDIV1_SHIFT = 12, 95 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 96 PLL_FBDIV_SHIFT = 0, 97 PLL_FBDIV_MASK = 0xfff, 98 99 /* PLLCON1 */ 100 PLL_PDSEL_SHIFT = 15, 101 PLL_PD1_SHIFT = 14, 102 PLL_PD_SHIFT = 13, 103 PLL_PD_MASK = 1 << PLL_PD_SHIFT, 104 PLL_DSMPD_SHIFT = 12, 105 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 106 PLL_LOCK_STATUS_SHIFT = 10, 107 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 108 PLL_POSTDIV2_SHIFT = 6, 109 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 110 PLL_REFDIV_SHIFT = 0, 111 PLL_REFDIV_MASK = 0x3f, 112 113 /* PLLCON2 */ 114 PLL_FOUT4PHASEPD_SHIFT = 27, 115 PLL_FOUTVCOPD_SHIFT = 26, 116 PLL_FOUTPOSTDIVPD_SHIFT = 25, 117 PLL_DACPD_SHIFT = 24, 118 PLL_FRAC_DIV = 0xffffff, 119 120 /* CRU_MODE */ 121 PLLMUX_FROM_XIN24M = 0, 122 PLLMUX_FROM_PLL, 123 PLLMUX_FROM_RTC32K, 124 USBPHY480M_MODE_SHIFT = 8, 125 USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT, 126 VPLL1_MODE_SHIFT = 6, 127 VPLL1_MODE_MASK = 3 << VPLL1_MODE_SHIFT, 128 VPLL0_MODE_SHIFT = 4, 129 VPLL0_MODE_MASK = 3 << VPLL0_MODE_SHIFT, 130 DPLL_MODE_SHIFT = 2, 131 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, 132 APLL_MODE_SHIFT = 0, 133 APLL_MODE_MASK = 3 << APLL_MODE_SHIFT, 134 135 /* CRU_CLK_SEL0_CON */ 136 CORE_ACLK_DIV_SHIFT = 12, 137 CORE_ACLK_DIV_MASK = 0x7 << CORE_ACLK_DIV_SHIFT, 138 CORE_DBG_DIV_SHIFT = 8, 139 CORE_DBG_DIV_MASK = 0xf << CORE_DBG_DIV_SHIFT, 140 CORE_CLK_PLL_SEL_SHIFT = 6, 141 CORE_CLK_PLL_SEL_MASK = 0x3 << CORE_CLK_PLL_SEL_SHIFT, 142 CORE_CLK_PLL_SEL_APLL = 0, 143 CORE_CLK_PLL_SEL_VPLL0, 144 CORE_CLK_PLL_SEL_VPLL1, 145 CORE_DIV_CON_SHIFT = 0, 146 CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, 147 148 /* CRU_CLK_SEL5_CON */ 149 BUS_PLL_SEL_SHIFT = 6, 150 BUS_PLL_SEL_MASK = 0x3 << BUS_PLL_SEL_SHIFT, 151 BUS_PLL_SEL_DPLL = 0, 152 BUS_PLL_SEL_VPLL0, 153 BUS_PLL_SEL_VPLL1, 154 BUS_ACLK_DIV_SHIFT = 0, 155 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 156 157 /* CRU_CLK_SEL6_CON */ 158 BUS_PCLK_DIV_SHIFT = 8, 159 BUS_PCLK_DIV_MASK = 0x1f << BUS_PCLK_DIV_SHIFT, 160 BUS_HCLK_DIV_SHIFT = 0, 161 BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT, 162 163 /* CRU_CLK_SEL8_CON */ 164 DCLK_VOP_SEL_SHIFT = 14, 165 DCLK_VOP_SEL_MASK = 0x3 << DCLK_VOP_SEL_SHIFT, 166 DCLK_VOP_SEL_DIVOUT = 0, 167 DCLK_VOP_SEL_FRACOUT, 168 DCLK_VOP_SEL_24M, 169 DCLK_VOP_PLL_SEL_SHIFT = 10, 170 DCLK_VOP_PLL_SEL_MASK = 0x3 << DCLK_VOP_PLL_SEL_SHIFT, 171 DCLK_VOP_PLL_SEL_DPLL = 0, 172 DCLK_VOP_PLL_SEL_VPLL0, 173 DCLK_VOP_PLL_SEL_VPLL1, 174 DCLK_VOP_DIV_SHIFT = 0, 175 DCLK_VOP_DIV_MASK = 0xff, 176 177 /* CRU_CLK_SEL25_CON */ 178 /* CRU_CLK_SEL26_CON */ 179 /* CRU_CLK_SEL27_CON */ 180 /* CRU_CLK_SEL28_CON */ 181 CLK_I2C_PLL_SEL_SHIFT = 14, 182 CLK_I2C_PLL_SEL_MASK = 0x3 << CLK_I2C_PLL_SEL_SHIFT, 183 CLK_I2C_PLL_SEL_DPLL = 0, 184 CLK_I2C_PLL_SEL_VPLL0, 185 CLK_I2C_PLL_SEL_24M, 186 CLK_I2C_DIV_CON_SHIFT = 0, 187 CLK_I2C_DIV_CON_MASK = 0x7f << CLK_I2C_DIV_CON_SHIFT, 188 189 /* CRU_CLK_SEL29_CON */ 190 CLK_PWM_PLL_SEL_SHIFT = 14, 191 CLK_PWM_PLL_SEL_MASK = 0x3 << CLK_PWM_PLL_SEL_SHIFT, 192 CLK_PWM_PLL_SEL_DPLL = 0, 193 CLK_PWM_PLL_SEL_VPLL0, 194 CLK_PWM_PLL_SEL_24M, 195 CLK_PWM_DIV_CON_SHIFT = 0, 196 CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT, 197 198 /* CRU_CLK_SEL30_CON */ 199 /* CRU_CLK_SEL31_CON */ 200 /* CRU_CLK_SEL32_CON */ 201 CLK_SPI_PLL_SEL_SHIFT = 14, 202 CLK_SPI_PLL_SEL_MASK = 0x3 << CLK_SPI_PLL_SEL_SHIFT, 203 CLK_SPI_PLL_SEL_DPLL = 0, 204 CLK_SPI_PLL_SEL_VPLL0, 205 CLK_SPI_PLL_SEL_24M, 206 CLK_SPI_DIV_CON_SHIFT = 0, 207 CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT, 208 209 /* CRU_CLK_SEL34_CON */ 210 CLK_SARADC_DIV_CON_SHIFT = 0, 211 CLK_SARADC_DIV_CON_MASK = 0x7ff << CLK_SARADC_DIV_CON_SHIFT, 212 213 /* CRU_CLK_SEL36_CON */ 214 PERI_PLL_SEL_SHIFT = 6, 215 PERI_PLL_SEL_MASK = 0x3 << PERI_PLL_SEL_SHIFT, 216 PERI_PLL_DPLL = 0, 217 PERI_PLL_VPLL0, 218 PERI_PLL_VPLL1, 219 PERI_ACLK_DIV_SHIFT = 0, 220 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 221 222 /* CRU_CLK_SEL37_CON */ 223 PERI_PCLK_DIV_SHIFT = 8, 224 PERI_PCLK_DIV_MASK = 0x1f << PERI_PCLK_DIV_SHIFT, 225 PERI_HCLK_DIV_SHIFT = 0, 226 PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT, 227 228 /* CRU_CLKSEL41_CON */ 229 EMMC_CLK_SEL_SHIFT = 15, 230 EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, 231 EMMC_CLK_SEL_EMMC = 0, 232 EMMC_CLK_SEL_EMMC_DIV50, 233 EMMC_PLL_SHIFT = 8, 234 EMMC_PLL_MASK = 0x3 << EMMC_PLL_SHIFT, 235 EMMC_SEL_DPLL = 0, 236 EMMC_SEL_VPLL0, 237 EMMC_SEL_VPLL1, 238 EMMC_SEL_24M, 239 EMMC_DIV_SHIFT = 0, 240 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 241 }; 242 243 check_member(rk3308_cru, emmc_con[1], 0x494); 244 245 #endif 246