1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_CRU_RK3308_H 7 #define _ASM_ARCH_CRU_RK3308_H 8 9 #include <common.h> 10 11 #define MHz 1000000 12 #define OSC_HZ (24 * MHz) 13 14 #define APLL_HZ (816 * MHz) 15 16 #define CORE_ACLK_HZ 408000000 17 #define CORE_DBG_HZ 204000000 18 19 #define BUS_ACLK_HZ 200000000 20 #define BUS_HCLK_HZ 100000000 21 #define BUS_PCLK_HZ 100000000 22 23 #define PERI_ACLK_HZ 200000000 24 #define PERI_HCLK_HZ 100000000 25 #define PERI_PCLK_HZ 100000000 26 27 #define AUDIO_HCLK_HZ 100000000 28 #define AUDIO_PCLK_HZ 100000000 29 30 /* RK3308 pll id */ 31 enum rk3308_pll_id { 32 APLL, 33 DPLL, 34 VPLL0, 35 VPLL1, 36 PLL_COUNT, 37 }; 38 39 struct rk3308_clk_info { 40 unsigned long id; 41 char *name; 42 }; 43 44 struct pll_rate_table { 45 unsigned long rate; 46 unsigned int fbdiv; 47 unsigned int postdiv1; 48 unsigned int refdiv; 49 unsigned int postdiv2; 50 unsigned int dsmpd; 51 unsigned int frac; 52 }; 53 54 /* Private data for the clock driver - used by rockchip_get_cru() */ 55 struct rk3308_clk_priv { 56 struct rk3308_cru *cru; 57 ulong apll_hz; 58 ulong dpll_hz; 59 ulong vpll0_hz; 60 ulong vpll1_hz; 61 }; 62 63 struct rk3308_cru { 64 struct rk3308_pll { 65 unsigned int con0; 66 unsigned int con1; 67 unsigned int con2; 68 unsigned int con3; 69 unsigned int con4; 70 unsigned int reserved0[3]; 71 } pll[4]; 72 unsigned int reserved1[8]; 73 unsigned int mode; 74 unsigned int misc; 75 unsigned int reserved2[2]; 76 unsigned int glb_cnt_th; 77 unsigned int glb_rst_st; 78 unsigned int glb_srst_fst; 79 unsigned int glb_srst_snd; 80 unsigned int glb_rst_con; 81 unsigned int pll_lock; 82 unsigned int reserved3[6]; 83 unsigned int hwffc_con0; 84 unsigned int reserved4; 85 unsigned int hwffc_th; 86 unsigned int hwffc_intst; 87 unsigned int apll_con0_s; 88 unsigned int apll_con1_s; 89 unsigned int clksel_con0_s; 90 unsigned int reserved5; 91 unsigned int clksel_con[74]; 92 unsigned int reserved6[54]; 93 unsigned int clkgate_con[15]; 94 unsigned int reserved7[(0x380 - 0x338) / 4 - 1]; 95 unsigned int ssgtbl[32]; 96 unsigned int softrst_con[10]; 97 unsigned int reserved8[(0x480 - 0x424) / 4 - 1]; 98 unsigned int sdmmc_con[2]; 99 unsigned int sdio_con[2]; 100 unsigned int emmc_con[2]; 101 }; 102 103 enum { 104 /* PLLCON0*/ 105 PLL_BP_SHIFT = 15, 106 PLL_POSTDIV1_SHIFT = 12, 107 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 108 PLL_FBDIV_SHIFT = 0, 109 PLL_FBDIV_MASK = 0xfff, 110 111 /* PLLCON1 */ 112 PLL_PDSEL_SHIFT = 15, 113 PLL_PD1_SHIFT = 14, 114 PLL_PD_SHIFT = 13, 115 PLL_PD_MASK = 1 << PLL_PD_SHIFT, 116 PLL_DSMPD_SHIFT = 12, 117 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 118 PLL_LOCK_STATUS_SHIFT = 10, 119 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 120 PLL_POSTDIV2_SHIFT = 6, 121 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 122 PLL_REFDIV_SHIFT = 0, 123 PLL_REFDIV_MASK = 0x3f, 124 125 /* PLLCON2 */ 126 PLL_FOUT4PHASEPD_SHIFT = 27, 127 PLL_FOUTVCOPD_SHIFT = 26, 128 PLL_FOUTPOSTDIVPD_SHIFT = 25, 129 PLL_DACPD_SHIFT = 24, 130 PLL_FRAC_DIV = 0xffffff, 131 132 /* CRU_MODE */ 133 PLLMUX_FROM_XIN24M = 0, 134 PLLMUX_FROM_PLL, 135 PLLMUX_FROM_RTC32K, 136 USBPHY480M_MODE_SHIFT = 8, 137 USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT, 138 VPLL1_MODE_SHIFT = 6, 139 VPLL1_MODE_MASK = 3 << VPLL1_MODE_SHIFT, 140 VPLL0_MODE_SHIFT = 4, 141 VPLL0_MODE_MASK = 3 << VPLL0_MODE_SHIFT, 142 DPLL_MODE_SHIFT = 2, 143 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, 144 APLL_MODE_SHIFT = 0, 145 APLL_MODE_MASK = 3 << APLL_MODE_SHIFT, 146 147 /* CRU_CLK_SEL0_CON */ 148 CORE_ACLK_DIV_SHIFT = 12, 149 CORE_ACLK_DIV_MASK = 0x7 << CORE_ACLK_DIV_SHIFT, 150 CORE_DBG_DIV_SHIFT = 8, 151 CORE_DBG_DIV_MASK = 0xf << CORE_DBG_DIV_SHIFT, 152 CORE_CLK_PLL_SEL_SHIFT = 6, 153 CORE_CLK_PLL_SEL_MASK = 0x3 << CORE_CLK_PLL_SEL_SHIFT, 154 CORE_CLK_PLL_SEL_APLL = 0, 155 CORE_CLK_PLL_SEL_VPLL0, 156 CORE_CLK_PLL_SEL_VPLL1, 157 CORE_DIV_CON_SHIFT = 0, 158 CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, 159 160 /* CRU_CLK_SEL5_CON */ 161 BUS_PLL_SEL_SHIFT = 6, 162 BUS_PLL_SEL_MASK = 0x3 << BUS_PLL_SEL_SHIFT, 163 BUS_PLL_SEL_DPLL = 0, 164 BUS_PLL_SEL_VPLL0, 165 BUS_PLL_SEL_VPLL1, 166 BUS_ACLK_DIV_SHIFT = 0, 167 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 168 169 /* CRU_CLK_SEL6_CON */ 170 BUS_PCLK_DIV_SHIFT = 8, 171 BUS_PCLK_DIV_MASK = 0x1f << BUS_PCLK_DIV_SHIFT, 172 BUS_HCLK_DIV_SHIFT = 0, 173 BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT, 174 175 /* CRU_CLK_SEL8_CON */ 176 DCLK_VOP_SEL_SHIFT = 14, 177 DCLK_VOP_SEL_MASK = 0x3 << DCLK_VOP_SEL_SHIFT, 178 DCLK_VOP_SEL_DIVOUT = 0, 179 DCLK_VOP_SEL_FRACOUT, 180 DCLK_VOP_SEL_24M, 181 DCLK_VOP_PLL_SEL_SHIFT = 10, 182 DCLK_VOP_PLL_SEL_MASK = 0x3 << DCLK_VOP_PLL_SEL_SHIFT, 183 DCLK_VOP_PLL_SEL_DPLL = 0, 184 DCLK_VOP_PLL_SEL_VPLL0, 185 DCLK_VOP_PLL_SEL_VPLL1, 186 DCLK_VOP_DIV_SHIFT = 0, 187 DCLK_VOP_DIV_MASK = 0xff, 188 189 /* CRU_CLK_SEL25_CON */ 190 /* CRU_CLK_SEL26_CON */ 191 /* CRU_CLK_SEL27_CON */ 192 /* CRU_CLK_SEL28_CON */ 193 CLK_I2C_PLL_SEL_SHIFT = 14, 194 CLK_I2C_PLL_SEL_MASK = 0x3 << CLK_I2C_PLL_SEL_SHIFT, 195 CLK_I2C_PLL_SEL_DPLL = 0, 196 CLK_I2C_PLL_SEL_VPLL0, 197 CLK_I2C_PLL_SEL_24M, 198 CLK_I2C_DIV_CON_SHIFT = 0, 199 CLK_I2C_DIV_CON_MASK = 0x7f << CLK_I2C_DIV_CON_SHIFT, 200 201 /* CRU_CLK_SEL29_CON */ 202 CLK_PWM_PLL_SEL_SHIFT = 14, 203 CLK_PWM_PLL_SEL_MASK = 0x3 << CLK_PWM_PLL_SEL_SHIFT, 204 CLK_PWM_PLL_SEL_DPLL = 0, 205 CLK_PWM_PLL_SEL_VPLL0, 206 CLK_PWM_PLL_SEL_24M, 207 CLK_PWM_DIV_CON_SHIFT = 0, 208 CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT, 209 210 /* CRU_CLK_SEL30_CON */ 211 /* CRU_CLK_SEL31_CON */ 212 /* CRU_CLK_SEL32_CON */ 213 CLK_SPI_PLL_SEL_SHIFT = 14, 214 CLK_SPI_PLL_SEL_MASK = 0x3 << CLK_SPI_PLL_SEL_SHIFT, 215 CLK_SPI_PLL_SEL_DPLL = 0, 216 CLK_SPI_PLL_SEL_VPLL0, 217 CLK_SPI_PLL_SEL_24M, 218 CLK_SPI_DIV_CON_SHIFT = 0, 219 CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT, 220 221 /* CRU_CLK_SEL34_CON */ 222 CLK_SARADC_DIV_CON_SHIFT = 0, 223 CLK_SARADC_DIV_CON_MASK = 0x7ff << CLK_SARADC_DIV_CON_SHIFT, 224 225 /* CRU_CLK_SEL36_CON */ 226 PERI_PLL_SEL_SHIFT = 6, 227 PERI_PLL_SEL_MASK = 0x3 << PERI_PLL_SEL_SHIFT, 228 PERI_PLL_DPLL = 0, 229 PERI_PLL_VPLL0, 230 PERI_PLL_VPLL1, 231 PERI_ACLK_DIV_SHIFT = 0, 232 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 233 234 /* CRU_CLK_SEL37_CON */ 235 PERI_PCLK_DIV_SHIFT = 8, 236 PERI_PCLK_DIV_MASK = 0x1f << PERI_PCLK_DIV_SHIFT, 237 PERI_HCLK_DIV_SHIFT = 0, 238 PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT, 239 240 /* CRU_CLKSEL41_CON */ 241 EMMC_CLK_SEL_SHIFT = 15, 242 EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, 243 EMMC_CLK_SEL_EMMC = 0, 244 EMMC_CLK_SEL_EMMC_DIV50, 245 EMMC_PLL_SHIFT = 8, 246 EMMC_PLL_MASK = 0x3 << EMMC_PLL_SHIFT, 247 EMMC_SEL_DPLL = 0, 248 EMMC_SEL_VPLL0, 249 EMMC_SEL_VPLL1, 250 EMMC_SEL_24M, 251 EMMC_DIV_SHIFT = 0, 252 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 253 254 /* CRU_CLK_SEL45_CON */ 255 AUDIO_PCLK_DIV_SHIFT = 8, 256 AUDIO_PCLK_DIV_MASK = 0x1f << AUDIO_PCLK_DIV_SHIFT, 257 AUDIO_PLL_SEL_SHIFT = 6, 258 AUDIO_PLL_SEL_MASK = 0x3 << AUDIO_PLL_SEL_SHIFT, 259 AUDIO_PLL_VPLL0 = 0, 260 AUDIO_PLL_VPLL1, 261 AUDIO_PLL_24M, 262 AUDIO_HCLK_DIV_SHIFT = 0, 263 AUDIO_HCLK_DIV_MASK = 0x1f << AUDIO_HCLK_DIV_SHIFT, 264 }; 265 266 check_member(rk3308_cru, emmc_con[1], 0x494); 267 268 #endif 269