1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_CRU_RK322X_H 7 #define _ASM_ARCH_CRU_RK322X_H 8 9 #include <common.h> 10 11 #define MHz 1000 * 1000 12 #define OSC_HZ (24 * MHz) 13 #define APLL_HZ (600 * MHz) 14 #define GPLL_HZ (1200 * MHz) 15 #define CPLL_HZ (500 * MHz) 16 #define ACLK_BUS_HZ (150 * MHz) 17 #define ACLK_PERI_HZ (150 * MHz) 18 19 /* Private data for the clock driver - used by rockchip_get_cru() */ 20 struct rk322x_clk_priv { 21 struct rk322x_cru *cru; 22 ulong gpll_hz; 23 ulong cpll_hz; 24 }; 25 26 struct rk322x_cru { 27 struct rk322x_pll { 28 unsigned int con0; 29 unsigned int con1; 30 unsigned int con2; 31 } pll[4]; 32 unsigned int reserved0[4]; 33 unsigned int cru_mode_con; 34 unsigned int cru_clksel_con[35]; 35 unsigned int cru_clkgate_con[16]; 36 unsigned int cru_softrst_con[9]; 37 unsigned int cru_misc_con; 38 unsigned int reserved1[2]; 39 unsigned int cru_glb_cnt_th; 40 unsigned int reserved2[3]; 41 unsigned int cru_glb_rst_st; 42 unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1]; 43 unsigned int cru_sdmmc_con[2]; 44 unsigned int cru_sdio_con[2]; 45 unsigned int reserved4[2]; 46 unsigned int cru_emmc_con[2]; 47 unsigned int reserved5[4]; 48 unsigned int cru_glb_srst_fst_value; 49 unsigned int cru_glb_srst_snd_value; 50 unsigned int cru_pll_mask_con; 51 }; 52 check_member(rk322x_cru, cru_pll_mask_con, 0x01f8); 53 54 enum rk322x_pll_id { 55 APLL, 56 DPLL, 57 CPLL, 58 GPLL, 59 NPLL, 60 PLL_COUNT, 61 }; 62 63 struct rk322x_clk_info { 64 unsigned long id; 65 char *name; 66 bool is_cru; 67 }; 68 69 #define RK2928_PLL_CON(x) ((x) * 0x4) 70 #define RK2928_MODE_CON 0x40 71 72 enum { 73 /* CRU_CLK_SEL0_CON */ 74 BUS_ACLK_PLL_SEL_SHIFT = 13, 75 BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, 76 BUS_ACLK_PLL_SEL_CPLL = 0, 77 BUS_ACLK_PLL_SEL_GPLL, 78 BUS_ACLK_PLL_SEL_HDMIPLL, 79 BUS_ACLK_DIV_SHIFT = 8, 80 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 81 CORE_CLK_PLL_SEL_SHIFT = 6, 82 CORE_CLK_PLL_SEL_MASK = 3 << CORE_CLK_PLL_SEL_SHIFT, 83 CORE_CLK_PLL_SEL_APLL = 0, 84 CORE_CLK_PLL_SEL_GPLL, 85 CORE_CLK_PLL_SEL_DPLL, 86 CORE_DIV_CON_SHIFT = 0, 87 CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 88 89 /* CRU_CLK_SEL1_CON */ 90 BUS_PCLK_DIV_SHIFT = 12, 91 BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, 92 BUS_HCLK_DIV_SHIFT = 8, 93 BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, 94 CORE_ACLK_DIV_SHIFT = 4, 95 CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, 96 CORE_PERI_DIV_SHIFT = 0, 97 CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, 98 99 /* CRU_CLKSEL5_CON */ 100 GMAC_OUT_PLL_SHIFT = 15, 101 GMAC_OUT_PLL_MASK = 1 << GMAC_OUT_PLL_SHIFT, 102 GMAC_OUT_DIV_SHIFT = 8, 103 GMAC_OUT_DIV_MASK = 0x1f << GMAC_OUT_DIV_SHIFT, 104 MAC_PLL_SEL_SHIFT = 7, 105 MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, 106 RMII_EXTCLK_SLE_SHIFT = 5, 107 RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SLE_SHIFT, 108 RMII_EXTCLK_SEL_INT = 0, 109 RMII_EXTCLK_SEL_EXT, 110 CLK_MAC_DIV_SHIFT = 0, 111 CLK_MAC_DIV_MASK = 0x1f << CLK_MAC_DIV_SHIFT, 112 113 /* CRU_CLKSEL10_CON */ 114 PERI_PCLK_DIV_SHIFT = 12, 115 PERI_PCLK_DIV_MASK = 7 << PERI_PCLK_DIV_SHIFT, 116 PERI_PLL_SEL_SHIFT = 10, 117 PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, 118 PERI_PLL_CPLL = 0, 119 PERI_PLL_GPLL, 120 PERI_PLL_HDMIPLL, 121 PERI_HCLK_DIV_SHIFT = 8, 122 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, 123 PERI_ACLK_DIV_SHIFT = 0, 124 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 125 126 /* CRU_CLKSEL11_CON */ 127 EMMC_PLL_SHIFT = 12, 128 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 129 EMMC_SEL_CPLL = 0, 130 EMMC_SEL_GPLL, 131 EMMC_SEL_24M, 132 SDIO_PLL_SHIFT = 10, 133 SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, 134 SDIO_SEL_CPLL = 0, 135 SDIO_SEL_GPLL, 136 SDIO_SEL_24M, 137 MMC0_PLL_SHIFT = 8, 138 MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, 139 MMC0_SEL_CPLL = 0, 140 MMC0_SEL_GPLL, 141 MMC0_SEL_24M, 142 MMC0_DIV_SHIFT = 0, 143 MMC0_DIV_MASK = 0xff << MMC0_DIV_SHIFT, 144 145 /* CRU_CLKSEL12_CON */ 146 EMMC_DIV_SHIFT = 8, 147 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 148 SDIO_DIV_SHIFT = 0, 149 SDIO_DIV_MASK = 0xff << SDIO_DIV_SHIFT, 150 151 /* CRU_CLKSEL26_CON */ 152 DDR_CLK_PLL_SEL_SHIFT = 8, 153 DDR_CLK_PLL_SEL_MASK = 3 << DDR_CLK_PLL_SEL_SHIFT, 154 DDR_CLK_SEL_DPLL = 0, 155 DDR_CLK_SEL_GPLL, 156 DDR_CLK_SEL_APLL, 157 DDR_DIV_SEL_SHIFT = 0, 158 DDR_DIV_SEL_MASK = 3 << DDR_DIV_SEL_SHIFT, 159 160 /* CRU_CLKSEL27_CON */ 161 DCLK_LCDC_PLL_SEL_GPLL = 0, 162 DCLK_LCDC_PLL_SEL_CPLL = 1, 163 DCLK_LCDC_PLL_SEL_SHIFT = 0, 164 DCLK_LCDC_PLL_SEL_MASK = 1 << DCLK_LCDC_PLL_SEL_SHIFT, 165 DCLK_LCDC_SEL_HDMIPHY = 0, 166 DCLK_LCDC_SEL_PLL = 1, 167 DCLK_LCDC_SEL_SHIFT = 1, 168 DCLK_LCDC_SEL_MASK = 1 << DCLK_LCDC_SEL_SHIFT, 169 DCLK_LCDC_DIV_CON_SHIFT = 8, 170 DCLK_LCDC_DIV_CON_MASK = 0xFf << DCLK_LCDC_DIV_CON_SHIFT, 171 172 /* CRU_CLKSEL29_CON */ 173 GMAC_CLK_SRC_SHIFT = 12, 174 GMAC_CLK_SRC_MASK = 1 << GMAC_CLK_SRC_SHIFT, 175 176 /* CRU_CLKSEL33_CON */ 177 ACLK_VOP_PLL_SEL_SHIFT = 5, 178 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT, 179 ACLK_VOP_PLL_SEL_CPLL = 0, 180 ACLK_VOP_PLL_SEL_GPLL = 1, 181 ACLK_VOP_PLL_SEL_HDMIPHY = 2, 182 ACLK_VOP_DIV_CON_SHIFT = 0, 183 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 184 185 /* CRU_SOFTRST5_CON */ 186 DDRCTRL_PSRST_SHIFT = 11, 187 DDRCTRL_SRST_SHIFT = 10, 188 DDRPHY_PSRST_SHIFT = 9, 189 DDRPHY_SRST_SHIFT = 8, 190 }; 191 #endif 192